APARNA MISHRA

Software Engineer

Delhi, India5 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in Digital VLSI Design and Memory Design.
  • Proficient in using ELDO and Virtuoso tools.
  • Strong background in RTL and Physical Design.
Stackforce AI infers this person is a Digital VLSI Design Engineer with expertise in Memory and Physical Design.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignPhysical Design

Other Skills

Static Timing AnalysisVerilogDFTMemoryC

About

Looking for opportunity to work in Digital VLSI Design,Memory Design and Test,Physical Design, DFT, RTL Design.Worked on various tools such as ELDO, Virtuoso(65nm and 180nm),Tempus,Conformal etc for various projects.

Experience

5 yrs 7 mos
Total Experience
5 yrs 7 mos
Average Tenure
5 yrs 7 mos
Current Experience

Qualcomm

4 roles

Senior Lead Engineer

Dec 2024 – Present · 1 yr 4 mos

Static Timing AnalysisRTL DesignVerilogPhysical DesignDFT

Senior Design Engineer

Promoted

Nov 2022 – Nov 2024 · 2 yrs

Design Engineer

Jul 2020 – Oct 2022 · 2 yrs 3 mos

Engineer Intern

Jan 2020 – Jun 2020 · 5 mos

Education

Indraprastha Institute of Information Technology, Delhi

Master of Technology - MTech — VLSI and Embedded system

Jan 2018 – Jan 2020

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