Shamin Mathews

Software Engineer

Bengaluru, Karnataka, India6 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in Universal Verification Methodology (UVM) and SystemVerilog.
  • Strong background in ASIC design and verification.
  • Proven track record in low power verification and formal tools.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and UVM methodologies.

Contact

Skills

Other Skills

VerilogCCadence VirtuosoVerdivisualizerRTL CodingRTL VerificationRTL DesignModelSimXilinxAltera QuartusDebuggingFormal Verification

About

Experienced Engineer with a demonstrated history of working in the semiconductor industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Perl,Tcl-Tk, I2C, ETHERNET and AMBA.Good knowledge on Formal tools, Low power Verification, GLS. Strong engineering professional with a Master of Technology - MTech focused in VLSI design from Vellore Institute of Technology. Currently working on Ethernet Verification.

Experience

6 yrs 7 mos
Total Experience
6 yrs 7 mos
Average Tenure
6 yrs 7 mos
Current Experience

Qualcomm

3 roles

Lead Engineer

Promoted

Nov 2025Present · 5 mos

Senior Engineer

Promoted

Nov 2022Dec 2025 · 3 yrs 1 mo

Engineer

Aug 2019Oct 2022 · 3 yrs 2 mos

  • works in peripheral IP verification

Mediatek

2 roles

Design Verification Engineer

Jun 2019Aug 2019 · 2 mos

Design Verification Engineer

Jul 2018Jun 2019 · 11 mos

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI design

Jan 2017Jan 2019

Govt college of engineering kannur

Jan 2012Jan 2016

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