Rajnish Garg

Software Engineer

Noida, Uttar Pradesh, India20 yrs 8 mos experience

Key Highlights

  • Expert in ASIC and CMOS technology development
  • Proficient in EDA tools and Verilog programming
  • Strong background in circuit design and debugging
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and CMOS technologies.

Contact

LinkedIn

Skills

Core Skills

AsicCmos

Other Skills

Circuit DesignDebuggingEDAPerlSemiconductorsTCLVerilog

Experience

Stmicroelectronics

Senior Design Engineer - STD cell Library

Jul 2005 – Present · 20 yrs 8 mos

  • To develop and support ASIC standard Cell Libraries for various CMOS technologies
ASICCMOSEDAVerilogSemiconductorsCircuit Design+3

Education

Punjab Engineering College

Jan 2001 – Jan 2005

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