May 2018 – Jun 2019 · 1 yr 1 mo · Tempe

• Worked primarily on RTL Design, Development & Verification of CNN layers for a custom Deep Learning Accelerator (IP)
• Provided microarchitecture definition, specification & implemented the RTL design of various blocks using System Verilog
• Implemented data & control protection on AXI interconnect, by developing ECC/parity encoder and decoder modules
• Developed Error Correction Code (ECC) protection schemes such as Hamming code (72,64), Hamming code (266,256) for SEC-DED (Single Error Correction, Double Error Detection) and Parity (per 16bits) Word for Error Detection
• Developed Error Injection capability (8-bit LFSR) for each AXI master & slave supporting Interconnect Data protection
• Led the Primetime-PX based power analysis (averaged & time-based) for the Deep Learning Accelerator subsystem
• Presented the detailed hierarchical power results to the frontend design team, which helped us to meet the Power requirement (<2 Watts), by implementing efficient clock-gating techniques across various blocks in the DLA core
• Performed functional simulation debug at block level & top-level using System Verilog Verification & UVM environment
• Developed module-level testbench & developed python scripts to generate inputs (.mifs) to initialize the buffers
• Performed module-level Spyglass Lint/Clock Domain Crossing (CDC) and elaboration checks as part of the design flow
• Single-handedly executed the task of on-chip memory (SRAMs/RFs) integration, generation & analysis based on the PPA (Power, Performance, Area) requirement for SoC subsystems using ARM’s Artisan Memory Compiler & Explorer
• Developed a Perl based custom automation flow for ARM memory generation & analysis based on user’s PPA requirement
• Developed boot sequence for the accelerator, configured RC oscillator to provide 1MHz boot clock, configured XTAL as a reference clock source to PLLs and programmed PLLs at different frequencies to provide AHB and accelerator core clocks

Aug 2017 – Apr 2018 · 8 mos

• Supervised lab projects involving design & simulation of circuits using EDA tools for graduate level course VLSI Design (EEE525).

May 2017 – Apr 2018 · 11 mos

• Developed & conceptualized ASIC implementation of deep convolutional neural networks in TSMCs 28nm technology. Implemented the layers of CNN algorithms in Verilog and performed the complete ASIC design flow: RTL Simulation (ModelSim), Synthesis (Synopsys DC Compiler) & Automatic Place and Route (Cadence Encounter & Innovus)

Aug 2016 – Apr 2018 · 1 yr 8 mos

May 2015 – Jul 2015 · 2 mos · Greater Delhi Area

• OBJECTIVE: Designed and developed a “modular and multifunctional” 3D printer, and automated the system by interfacing different types of sensors which expunged the most common 3D printer issues.
• INNOVATIONS: Introduced magnetic joint assembly to produce a unique and attractively designed machine and reduced backlash errors. The conventional fasteners and complex hinges were replaced by magnetic joints by which we could attach a number of interchangeable modules to the end-effector (eg. 2D plotter, laser engraver, pcb engraver, pick and place & wood burner). Developed an auto-detect filament sensor to eliminate “filament run out” and “tangling” issues during 3D printing. Created an “auto bed-levelling” mechanism which reduced the calibration time and the need of any human intervention. Built a modular enclosure for the electronics section, which could be easily be replaced in case of frequent defects or failures.
• IMPACT: The “magnetic joint” system considerably improved the print speed (around 3 times faster) with a greater accuracy. Improvement and modification in the design resulted in producing a multifunctional 3D machine. It is a low cost, user friendly, easy to calibrate, and a maintenance friendly machine. An extensive research was made on component optimization which considerably reduced the cost by 50% of the current 3D printers used by LBD Makers and made it compatible for the common users and schools.

Jul 2014 – Mar 2015 · 8 mos · IIT Kanpur

• Led a team of 6 coordinators and 15 secretaries for the conduction of 4 events under ECDC. Structured and implemented event preparation and execution with the help of these subordinates. Replaced an existing event which saw less participation last year with a fresh and more dynamic event (Electrade). Managed the successful conduction of “Zonal Prelims” and “Workshops” across different colleges of India. Conducted "Techkriti Open School Championship” for the students from classes 9th to 12th for the first time in India.
• Modification in the event structure, boosted the participation figures by more than 55 percent of last year. The new event (Electrade) was made one of the Flagship events of Techkriti 2015, which was unprecedented for ECDC.

Jul 2012 – Jun 2016 · 3 yrs 11 mos · Greater Lucknow Area