Sreeram Chandrasekar

Product Engineer

Bengaluru, Karnataka, India26 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led teams to deliver industry-leading ARM CPU implementations.
Developed automated power integrity closure flows for major clients.
Achieved first pass silicon success on OMAP SOCs.

Stackforce AI infers this person is a Semiconductor Engineering Leader with expertise in high-performance SoC design.

Contact

Skills

Core Skills

SocAsicPower IntegrityTiming Closure

Other Skills

Machine LearningHigh performance design closureAutomationARM CPUARM CPU subsystemsDesign flow methodologyOMAP IP coresSignoff methodologiesSOC ImplementationSilicon ValidationCrosstalk MitigationStatic Timing AnalysisPhysical DesignEDAProject Management

About

- Leadership across Design execution and CAD/Methodology, focused on Implementation (RTL2GDS) and Signoff - Synthesis, P&R, PPA / Design Closure, Timing & Power Integrity Signoff - Led teams to deliver Industry leading High Performance and Low power implementations, for ARM CPUs, GPUs, Video/ Imaging cores, Memory subsystems and SOC top level, for Mobile Apps Processor SOCs - Built and led strong technical teams focused on Innovation And Execution

Experience

26 yrs 3 mos

Total Experience

8 yrs 9 mos

Average Tenure

11 yrs

Current Experience

Cadence design systems

Product Engineering

May 2015 – Present · 11 yrs · Bengaluru Area, India

Lead product engineering for Machine Learning, Power Integrity and High performance design closure domains
Exploring / exploiting ML application at various levels in the digital implementation flow (Check out http://cadence.com/go/cerebrus)
Developed Fully automated power integrity closure flows, deployed at several major customer flows in production
Built high performance PE team that specializes in Design closure / PPA push, and works with strategic customer partners on high performance CPU / GPU / SOC / Foundry engagements
Our team establishes the reference flows for high performance and low power implementation of ARM CPU subsystems (Generic version available as RAKs - https://www.cadence.com/en_US/home/solutions/arm-based-solutions/arm-based-soc-implementation/arm-rak.html )

Machine LearningPower IntegrityHigh performance design closureSoCASIC

Mediatek

Senior Member of Technical Staff & CPU Manager

Apr 2013 – Jan 2015 · 1 yr 9 mos · Austin, Texas Area

Owned delivery of multiple derivative configurations of high performance ARM CPU subsystems concurrently. Defined the flow / methodology for efficient design and delivery of such configurations
Established the work flows for definition and integration of Structured Data Paths in high performance ARM CPUs

ARM CPU subsystemsDesign flow methodologySoC

Texas instruments

Senior Member of Technical Staff (SMTS) & Design Manager

Jun 1999 – Dec 2012 · 13 yrs 6 mos · Bengaluru Area, India

OMAP IP cores (CPU, GPU, Video, DDR etc.) and SOC*
As Cores/IP Manager, delivered multiple generations of ARM CPUs, IMG GPUs, TI Video/Imaging cores with leadership PPA
As SOC Implementation Manager, successfully delivered first pass Silicon success on OMAP SOCs
Worked closely with library and process technology teams to enable the best Performance & Power for OMAP products
CAD/Meth for implementation, signoff, timing margins, power integrity etc.*
As leader of task force for Signoff, defined signoff methodologies and Specs for timing margins, power integrity etc.
Worked closely with Test/Product engineering teams to optimize the timing closure requirements for tester conditions, test power reduction
As part of Signoff CAD team, helped develop timing closure flows to fix Crosstalk noise / Crosstalk delay timing violations, and to develop, qualify and deploy SSTA and signoff extraction flows.

OMAP IP coresSignoff methodologiesTiming closureSoCASIC