Vaibhav Mustilwar

Product Engineer

Gadchiroli, Maharashtra, India1 yr 7 mos experience

Key Highlights

  • Experienced in VHDL and Static Timing Analysis.
  • Strong background in Agile Project Management.
  • Hands-on experience with Verilog and CDC.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VHDL and Static Timing Analysis.

Contact

Skills

Core Skills

VhdlStatic Timing AnalysisAgile Project Management

Other Skills

CDCVerilogGroup WorkC (Programming Language)C++Python (Programming Language)Collaborative Problem Solving

Experience

Qualcomm

Associate DFT Engineer

Aug 2024Present · 1 yr 7 mos · Bangalore Urban, Karnataka, India · On-site

VHDLStatic Timing AnalysisCDCVerilog

Logic fruit technologies

Research And Development Intern

Jan 2024Jul 2024 · 6 mos · Bengaluru, Karnataka, India · On-site

VHDLStatic Timing Analysis

Qualcomm

Internim Engineering Intern, Hardware

Jun 2023Aug 2023 · 2 mos · Bengaluru, Karnataka, India · On-site

Agile Project ManagementGroup Work

Education

Indian Institute Of Information Technology Allahabad

Bachelor of Technology - BTech

Dec 2020May 2024

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