Sai Seshagiri Rao B V — Software Engineer

• Have Experience in different Technology nodes like 7nm, 10nm, 14nm, 20nm, 22nm and 28nm in Physical Verification and Physical Design. • Handled responsibilites like reviewing Final Checks for Physical Verification Sign off and training new joiners. • Have Expeirnce in handling all Physical Verification Sign Off checks in different Foundires like TSMC/SAMSUNG/INTEL. • Have Theorital and Hands-On Experience in LVS/DRC/ERC/Antenna, DFM Related checks (Pattern Check & Litho checks) and Netlist Based Checks (PERC & ESD). • Have good Exposure to Double Pattern (DPT), Triple Pattern (TPT) & QPT violations. • Acheived experience in handling Complex Hard Macro’s and managing a team. • Have Hands-On Experience in understanding and implementing Timing ECO’s. • Have Experience in Floor Plan and understanding of Congestion areas maps.

Stackforce AI infers this person is a Physical Design and Verification Engineer with expertise in semiconductor technology.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 4 mos