Vikas Verma — Software Engineer

With over 12+ years of experience in Physical Design implementation at both block and full-chip SoC levels, I have contributed to the successful tape-out of multiple chips at the latest technology nodes. My expertise spans the complete execution of SoC design, including: - Floor-planning, Partitioning, and Power Planning - Place & Route (PnR), Clock Tree Synthesis (CTS), and Timing Closure - Static Timing Analysis (STA), Signal Integrity (SI) Analysis, and ECO Implementation - Physical Verification (DRC, LVS, ERC) and Low-Power Design Techniques I specialize in handling high-utilization, high-performance blocks and full-chip designs, ensuring robust and manufacturable solutions. Passionate about tackling complex challenges, I thrive in both independent and collaborative environments, driving projects from Netlist to GDSII with a focus on quality and efficiency.

Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in ASIC and SoC development.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 5 mos