Sourav Kumar Rana — DevOps Engineer
Senior RTL / FPGA Design Engineer | CXL 2.0/3.0 | PCIe Gen6 | Micro-Architecture RTL Design Engineer with 4+ years of experience architecting and implementing high-speed protocol IPs including CXL (2.0 / 3.0 – CXL.MEM & CXL.CACHE) and PCIe Gen6 (DLL layer). I specialize in: Micro-architecture definition & block ownership Multi-clock domain designs & CDC resolution Arbitration, Credit Mechanisms, Replay Buffers, CRC/FEC, Flit Packing FPGA bring-up, ILA debugging & timing closure Python/TCL automation for validation Currently working as Module Lead – RTL Design at Logic Fruit Technologies, leading CXL 3.0 development, mentoring engineers, and driving IP from specification to FPGA validation and customer milestones. I enjoy solving complex protocol and architecture problems, optimizing performance, and building scalable, reusable RTL IPs. Open to opportunities in: ASIC / SoC RTL Design | High-Speed Interfaces | CXL | PCIe | Data Center | AI/Accelerator Silicon
Stackforce AI infers this person is a specialist in high-speed interface design within the Data Center industry.
Location: Delhi, India
Experience: 4 yrs 5 mos
Skills
- Rtl Design
- Fpga Development
- Cxl
Career Highlights
- Expert in high-speed protocol IP design.
- Led CXL 3.0 development at Logic Fruit Technologies.
- Strong background in FPGA design and validation.
Work Experience
Logic Fruit Technologies
Lead Engineer (1 yr 10 mos)
R&D FPGA Engineer (2 yrs 1 mo)
R&D FPGA Engineer Trainee (6 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Information Technology Kota
Matriculate at Modern Delhi Public School Faridabad
High School at Saint Mary's Convent School, Ghaziabad
