S

Siddhant Kaashikar

Product Engineer

Pune, Maharashtra, India2 yrs 2 mos experience

Key Highlights

  • Expert in image processing and FPGA design.
  • Proficient in MATLAB and digital circuit design.
  • Strong background in adaptive systems and control.
Stackforce AI infers this person is a skilled engineer in Electronics and Automotive sectors, focusing on image processing and digital design.

Contact

Skills

Core Skills

EthernetImage ProcessingAdaptive Cruise ControlSimulationDigital DesignCircuit Design

Other Skills

Universal Asynchronous Receiver/Transmitter (UART)MIPII2CSimulinkRoad RunnerElectronic Control UnitMATLABUnreal Engine 4Digital Image ProcessingPrincipal Component AnalysisImage CompressionXilinx VivadoRISCVerilogMIPS

Experience

Visual information processing lab

Graduate Student Researcher

Jan 2026Present · 2 mos · Bengaluru, Karnataka, India · On-site

Logic fruit technologies

2 roles

Senior Research And Development Engineer

May 2025Jul 2025 · 2 mos · On-site

Research And Development Engineer

Jun 2023Jun 2025 · 2 yrs · On-site

  • 1. Configured camera.
  • 2. Created the test environment to simulate and validate image processing IPs on FPGA.
  • 3. Designed, simulated and validated 10/40/100 Gbps Ethernet stack IP from scratch on FGPA.
  • 4. Enhanced 10G Ethernet MAC IP code.
  • 5. Enhanced EtherCAT IP at 100/1000 Mbps.
Universal Asynchronous Receiver/Transmitter (UART)MIPII2CEthernetImage Processing

Bosch global software technologies

Intern

Jan 2022May 2022 · 4 mos · Bangalore Urban, Karnataka, India

  • Worked on the hardware and software architectures of ultrasonic sensors system in parking assistance
  • systems.
  • Co-simulated adaptive cruise control system on Unreal Engine, Simulink, MATLAB and RoadRunner
SimulinkRoad RunnerElectronic Control UnitMATLABAdaptive Cruise ControlUnreal Engine 4+1

Indian institute of technology, tirupati

IAS Summer Research Fellow

Jun 2021Sep 2021 · 3 mos · Tirupati, Andhra Pradesh, India · Remote

  • Learned about Image filtering, Image compression and Principal Component Analysis (PCA). Did the following during this fellowship:
  • 1. Designed Ideal, Gaussian and Butterworth filters of types Low pass, High pass, Band pass and Band reject using MATLAB.
  • 2. Developed an algorithm to find the dominant direction of a binary image using Principal Component Analysis (PCA) on MATLAB.
  • 3. Developed an algorithm for Image compression in frequency domain as well as by using Principal Component Analysis (PCA) using MATLAB.
Digital Image ProcessingPrincipal Component AnalysisMATLABImage CompressionImage Processing

Indian institute of technology, mandi

Research Intern

Jun 2021Aug 2021 · 2 mos · Mandi, Himachal Pradesh, India · Remote

  • Designed gate level 16 bit ALU and MIPS using Verilog on Xilinx Vivado.
Xilinx VivadoRISCVerilogMIPSDigital Design

Indian institute of technology, ropar

Summer Research Intern

May 2021Jul 2021 · 2 mos · Rupnagar, Punjab, India · Remote

  • Designed two stage CMOS Operational Transconductance Amplifier (OTA) with four different compensation techniques using SCL 180nm technology. Then using this OTA designed a Low Drop Out (LDO) voltage regulator. Simulation of the circuit was carried out on Cadence Virtuoso.
Cadence VirtuosoVoltage RegulatorsOperational AmplifierCircuit Design

Education

Indian Institute of Science (IISc)

Master of Technology - MTech — Artificial Intelligence

Jul 2025Jul 2027

Indian Institute of Information Technology Una

Bachelor of Technology - BTech — Electronics and Communications Engineering

Aug 2019May 2023

Savitribai Phule Pune University

Bachelor of Engineering - BE — Electronics and Telecommunication Engineering

Jan 2018Jan 2019

Kendriya Vidyalaya

Jan 2008Jan 2018

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