Jan 2022 – Feb 2025 · 3 yrs 1 mo · Paris, Île-de-France, France · On-site

• General context:
• Squarepoint Capital is an established investment manager committed to achieving high quality returns for their clients.
• I was part of the FPGA team.
• Missions:
• Design and development of a complete FPGA-based tick-to-trade system
• Various asset classes & exchanges
• System design
• Micro-architecture
• RTL coding
• Simulation
• Physical implementation
• On-board testint
• Production issues investigating and fixing
• Promoting FPGA engineering good practices in the team
• Introducing FPGA technology to interested engineers in other teams

Nov 2018 – Dec 2021 · 3 yrs 1 mo · Greater Paris Metropolitan Region · On-site

• General context:
• Scortex deploys artificial intelligence in the heart of factories. Our Quality Intelligence Solution enables manufacturing companies to take control of their quality:
• Automate complex visual inspection tasks at any stage of the manufacturing process
• Monitor key quality data through innovative dashboards
• Improve the production process by consolidating production knowledge
• I was in charge of the FPGA computation platform powering our product.
• Missions:
• Design and development of an FPGA computation platform
• High performance deep neural network inference engine
• Library of traditional computer vision functions
• Framework allowing building custom computation graphs
• Scalable platform allowing single-FPGA to many-FPGA applications
• Python API for data transfer, programming, configuration and monitoring
• Interface with AI team, product team & industrialisation team
• Design and development of industry automation features of our product
• Standard automation for interfaces with hardware, with software and with factory
• Custom automation for special machines deployed in factories
• Support of major PLC providers (Schneider, Siemens, Wago, etc.)
• Support of industry protocols (OPC-UA, ProfinetIO, ModbusTCP, etc.)

Feb 2017 – Aug 2018 · 1 yr 6 mos · Greater Paris Metropolitan Region · On-site

• General context:
• GrAI Matter Labs builds ultra-low power, fully programmable neuromorphic computing for sensor analytics and machine learning; powered by brain-inspired technology; to bring AI to every device on the edge.
• I was in charge of building our FPGA platform.
• Missions:
• Development from scratch of our FPGA platform
• Definition of the system architecture
• Definition of the microarchitecture of each computation core
• Development, integration and verification of the entire FPGA demonstration platform
• Implementation of the debugging infrastructure
• Development of the system configuration and monitoring software
• Communication with other teams involved in the project
• compiler team for generation of binaries
• application team for development of system demonstration applications
• suppliers for integration of sensors

Jun 2016 – Jan 2017 · 7 mos · Greater Paris Metropolitan Region · On-site

• General context:
• Celoxica designs financial data processing solutions leveraging FPGAs to achieve ultra-low latency, deterministic latency and ultra-high throughput.
• These systems perform input packet reception and filtering, data decoding and decompression, data normalization, financial computations and data enrichment and output messages formatting and publication.
• I was team leader for all hardware trading product development.
• Missions:
• Development of a new line of product from scratch
• Solution for pre-trade risk control
• Get and understand specifications of each exchange data protocol
• Specify architecture of the solution
• Develop and verify all modules, from scratch
• Integrate the entire solution, verify the functionality
• Write the testbench
• Write the test plan, the unit test library and verify the module
• Oversee feedhandler development
• Coaching of a junior engineer

Sep 2014 – May 2016 · 1 yr 8 mos · Greater Paris Metropolitan Region · On-site

• General context:
• Celoxica designs financial data processing solutions leveraging FPGAs to achieve ultra-low latency, deterministic latency and ultra-high throughput.
• These systems perform input packet reception and filtering, data decoding and decompression, data normalization, financial computations and data enrichment and output messages formatting and publication.
• I was project manager for the development of feedhandlers.
• Missions:
• Analysis and continuous enhancement of existing architecture
• Study existing architecture
• Suggest and implement architecture enhancements
• Develop feedhandlers for new exchanges (project manager)
• Get and understand specifications of each exchange data protocol
• Specify how our feedhandler shall process the data, validate with clients
• Develop new modules when necessary
• Integrate the entire feedhandler, verify the functionality
• Synthesize and fix timing issues
• Provide support after release
• Implement functional evolutions requested by clients
• Develop internal tools to increase productivity

Jan 2010 – Sep 2014 · 4 yrs 8 mos · Greater Paris Metropolitan Region · On-site

• General context:
• NovaSparks designs financial data processing solutions leveraging FPGAs to achieve ultra-low latency, deterministic latency and ultra-high throughput.
• These systems perform input packet reception and filtering, data decoding and decompression, data normalization, financial computations and data enrichment and output messages formatting and publication.
• I was in charge of various development in our R&D.
• Missions:
• Develop feedhandlers for new exchanges (project manager)
• Get and understand specifications of each exchange data protocol
• Specify how our feedhandler shall process the data, validate with clients
• Develop new modules when necessary
• Integrate the entire feedhandler, verify the functionality
• Synthesize and fix timing issues
• Provide support after release
• Implement functional evolutions requested by clients
• Develop our order book building module (key module of our solution) (project manager)
• Specify architecture with our CTO
• Implement the module
• Write the testbench
• Write the test plan, the unit test library and verify the module
• Provide support to any user of the module
• Investigate and fix bugs
• Develop new features requested by clients
• Develop internal tools to increase productivity
• Develop our latency measurement solution
• Develop a London-Frankfurt ultra-low-latency data link
• Develop a data bus monitoring IP
• Develop our network latency monitoring solution
• Develop our internal latency measurement solution (FPGA input to FPGA output, also FPGA input to software callback)
• Develop our PCIe connectivity solution
• Build the PCIe link and transmit data to server
• Develop the driver and the API
• Develop additional features (DMA, ping, latency measurement, etc.)
• Coach 2 engineers

Jan 2010 – Jan 2010 · 0 mo · Greater Paris Metropolitan Region · On-site

• Teaching assistant during lab sessions acquainting 4th-year students with circuit description in VHDL.
• (6 hours)

Jan 2010 – Jan 2010 · 0 mo · Greater Amiens Area · On-site

• Teaching assistant during lab sessions acquainting 4th-year students with OS programming in C programming language.
• (24 hours)

Aug 2009 – Dec 2009 · 4 mos · Greater Paris Metropolitan Region · On-site

• General context:
• Parrot is a french company that produces wireless communication systems such as hands-free kits, speakers or drones.
• I was in charge of verifying the P6i, a SoC designed by Parrot and embedded in all of its products.
• Missions:
• Verify the memory controller
• Verify the initialisation sequence of the controller
• Verify memory accesses
• Verify various operating modes of the controller (DDR & SDR)
• Verify the Power-On-Reset sequence of the SoC
• Verify the serial communication peripherals
• Verify the SPI controller
• Verify the I²C controller
• Verify the UART controller
• Verify the low-power modes of the SoC

Nov 2008 – Jul 2009 · 8 mos · Greater Paris Metropolitan Region · On-site

• General context:
• MBDA is a weapon manufacturer that produces missile and counter-measures systems.
• The "DDM-NG" system is a missile detector embarked on the Rafale fighter aircraft that records surroundings in the infra-red domain so as to detect missile trails.
• I was in charge of developing an image processing module part of this system.
• Missions:
• Review and validate the specification with the client
• Implement the module
• Write the testbench, the test library and verify the module
• Synthesize the module and check resource usage
• Write the architecture documentation

Feb 2008 – Oct 2008 · 8 mos · Greater Paris Metropolitan Region · On-site

• General context:
• Vejle is an IBM 45nm chip integrating 3 CPUs and a GPU, used in the Microsoft Xbox360.
• I was in charge of verifying the self-test engines of the chip (logic self-test engines, memory self-test engines, JTAG scan chains, production line scan chains).
• Missions:
• Understand the test features of the chip
• Retrieve, understand and update existing tests for the CPU
• Complete the test library for the GPU
• Write the test documentation

Nov 2007 – Jan 2008 · 2 mos · Greater Paris Metropolitan Region · On-site

• General context:
• Thales Avionics provides several flight control systems embeded in the Airbus A320: SEC, FAC and FMGC.
• These computers communicate using the ARINC429 protocol.
• I was in charge of implementing an ARINC429/Manchester transcoder with a lightning surge filter.
• Missions:
• Implement the transcoding
• Implement the lightning surge filter
• Write the testbench and verify the transcoder
• Write the architecture documentation

Apr 2007 – Aug 2007 · 4 mos · Greater Grenoble Metropolitan Area · On-site

• General context:
• Present wireless communication protocols require bandwith of several hundred MHz.
• From this perspective, France Telecom R&D has developped and advanced, reconfigurable, high throughput and low power OFDM modulator.
• I was in charge of prototyping this modulator on FPGA.
• Missions:
• Study the Xilinx Virtex 4 FPGA
• Implement and verify the computation modules
• Implement and verify the reconfigurable FFT matrix
• Implement and verify the control logic
• Integrate the entire modulator
• Write the testbench and verify the modulator
• Write the architecture documentation

Jun 2006 – Jul 2006 · 1 mo · Greater Grenoble Metropolitan Area · On-site

• General context:
• Mutek is a micro-kernel used by many research projects as operating system for mono or multi processor, homogenous or heterogenous systems.
• It was ported onto sevral architectures such as MIPS, ARM or PowerPC.
• I was in charge of porting this micro-kernel on the MicroBlaze (a 32bit Xilinx FPGA processor).
• Missions:
• Build a MicroBlaze platform
• Port low-level functions of the kernel
• Run a demonstration software on the platform