Kamal Krishna Kota

Software Engineer

Bengaluru, Karnataka, India11 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 4 years of ASIC verification experience
  • Expertise in SV-UVM/OVM methodologies
  • GATE topper with AIR 14th rank
Stackforce AI infers this person is a Semiconductor Verification Engineer with strong expertise in ASIC design and verification methodologies.

Contact

Skills

Core Skills

Asic VerificationFunctional Verification

Other Skills

ASICCEthernetEthernet protocolLinuxMAC and Ethernet Switch VerificationMakeModelSimOVMPERLShellShell ScriptingSystem VerilogTclUVM

About

ASIC Verification Engineer with 4 years of experience in verification using SV-UVM/OVM methodology. Was part of 5 ASIC verification projects. --> Created a OVM based Test Bench Architecture and developed Test Plan to verify IEEE 802.3 10G MAC. -->Was part of Functional verification of IEEE 802.3Q Ethernet switch. -->Expertise in verification using SV-OVM/UVM methodology. -->Expertise in automation using PERL and Tcl scripting. -->Have good command on working in Linux Environment. -->Have knowledge on the protocols related to Ethernet. My Technical skill set include: ->HVLs: System Verilog ->Methodologies: OVM, UVM ->HDLs: Verilog ->Scripting: PERL, Tcl ->Linux, Shell scripting ->Simulators: Modelsim/Questasim ->Protocols: IEEE 802.1D,Q (Bridge and VLANs), IEEE 802.3 Ethernet, MAC, XGMII, SGMII I am a GATE topper with AIR 14th rank in GATE 2013. I have good analytical skills, and I believe I can be valuable for any ASIC Verification projects.

Experience

Nvidia

senior asic verification engineer

Jun 2018Present · 7 yrs 9 mos · Bengaluru, Karnataka, India

System VerilogOVMUVMPERLTclLinux+2

Juniper networks

ASIC Verification Engineer

Jun 2015Jun 2018 · 3 yrs · Bengaluru Area, India

Vitesse semiconductor is now microsemi

2 roles

ASIC Verification Engineer

Jan 2014Jan 2015 · 1 yr · Hyderabad Area, India

  • I have created a OVM based hierarchical, reusable, Constrained randomized, TLM level testbench whcih covers the entire functionality of MAC10G Kernel.
  • And, I have also worked on Seville2 Ethernet switch core, which has a legacy PERL, Tcl testbench. Modified, the testbench to suit for Seville2, and implemented testcases to test the entire functionality block by block.
System VerilogOVMTclPERLASIC VerificationFunctional Verification

Intern - ASIC Verification Engineer

Jan 2014Jun 2014 · 5 mos · Hyderabad Area, India

  • I have learned,
  • System Verilog, Verilog,
  • OVM, UVM
  • Perl, Tcl, Shell, Make,
  • Linux, and ethernet standards as an intern.
System VerilogVerilogOVMUVMPERLTcl+3

Education

JNTU college of Engineering, Hyderabad

Master’s Degree — Communication and Signal processing

Jan 2012Jan 2014

JNTU college of Engineering Hyderabad

Bachelor’s Degree — Electronics and Communication Engineering

Jan 2009Jan 2013

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