Ritesh K

Software Engineer

Bengaluru, Karnataka, India9 yrs 7 mos experience

Highly Stable

Key Highlights

Over 10 years of VLSI front-end verification experience.
Expertise in NVMe based SSD product line and memory subsystems.
Proficient in SV and UVM based verification methodologies.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in VLSI and NVMe technologies.

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Skills

Core Skills

NvmeVerification

Other Skills

SV host firmwareflash modelNVMe based IPtestbench bring upRTL release supportend to end command flow debuggingtestbench scalabilityBlock-level verificationISR writingreset flow implementationreset testingTest plan developmentSV codingUVM based test case codingcode coverage

About

A Motivated, team-oriented, and responsible Verification Engineer having 10+ years of experience in VLSI front-end verification, possessing excellent technical, programming, and debugging skills. Technical Skills: ★ Proficient experience in NVMe based SSD product line, coherancy based memory sub-sytem that interacts with GPU/CPU/PCIE/CXL. ★ Experienced in testbench development, checker implementation, test case writing, code coverage, functional coverage, and constrained random verification in SV, UVM based environment. ★ Hands-on Experience with Cadence NCSIM/ Xcelium, Simvision, IMC tool, VCS, Verdi, etc

Experience

Nvidia

Senior Verification Engineer

Nov 2021 – Present · 4 yrs 4 mos · Bangalore Urban, Karnataka, India

Samsung semiconductor india

4 roles

Staff Engineer (Technical Lead)

Promoted

Mar 2020 – Nov 2021 · 1 yr 8 mos

★ Ownership for SV host firmware and flash model for NVMe based IP.
★ FW enhancement to support multiple host and flash cores.
★ Abort flow implementation and its testing on NVMe based IP.
★ Involved in activities like testbench bring up, RTL release support, end to end command flow debugging, critical check addition that captured many RTL bugs in a short spam.
★ Improved testbench scalability to reuse same testbench across multiple projects.

SV host firmwareflash modelNVMe based IPtestbench bring upRTL release supportend to end command flow debugging+3

Associate Staff Engineer/ Lead Engineer

Mar 2018 – Feb 2020 · 1 yr 11 mos

★ Block-level verification for SRAM interconnect.
★ ISR writing for complete IP
★ Reset flow implementation and reset testing on NVMe based IP.
★ Verification of critical modules that interact with FW.

Block-level verificationISR writingreset flow implementationreset testingNVMe based IPVerification+1

Senior Hardware Engineer

Jul 2016 – Feb 2018 · 1 yr 7 mos

★ Test plan development, SV, UVM based test case coding for NVMe based controller IP.
★ Verification closure with code coverage and functional coverage.

Test plan developmentSV codingUVM based test case codingcode coveragefunctional coverageVerification+1