Jun 2019 – Aug 2020 · 1 yr 2 mos · Hyderabad Area, India

• Designing External Peripheral Controller to work as Master Interface for enabling data transfers from (mem to mem/mem to aux/aux to mem) by treating the CPU core as Slave Interface.
• Enhanced APB and ATB Debug Interface working on APB clock with respect to earlier Core-clock/Trace-clock and clock-enable design. Modified SDC constraints to remove earlier multicycle paths and updated I/O constraints.
• Developed Multi-threading (multiple register file) and extended Data/Instruction memory support for higher performance.

Jun 2016 – May 2019 · 2 yrs 11 mos · Hyderabad Area, India

• Developed the Spyglass Linting Methodology for ARC Processors (ARC600, ARC700, EM and HS processors). Added new goals and rules to the existing Spyglass Lint Methodology to detect critical violations in the RTL Design.
• Automated the Spyglass Lint, CDC, DFT and timing violations in Perl to perform the design checks with the latest checked-in RTL files from designers.
• Defined micro-architecture and High Level Architecture for WIDE Memory Bus Interface (128 Bit Support) to enhance the design and performance requirements minimizing the power and gate count.
• Designed the Safety Logic for CNN EV (ARC Processors) by enabling the lockstep and diagnostic coverage mode.
• Worked on FMEDA (Failure modes, effects, and diagnostic analysis) for ASIL D Certification of HS Cores. Defined the failure modes for each sub-block unit and injected faults at outputs and traced it back to the final stage to find the erroneous/corrupted data.
• Worked on writing Design Assertions in order to check for logical bugs and inaccurate models in the design for EM Cores.
• Currently working on the Safety Logic for VDSP Processor and Cluster Level DMA Unit.

Aug 2013 – May 2016 · 2 yrs 9 mos

• I have been selected as Teaching Assistant for six concurrent semester in IIIT-H. The position held for various courses are listed in chronological order.
• (Aug,13 - Dec, 13) - Teaching Assistant for Linear electronic circuits course. Linear Electronics Circuits involves basic of diodes and BJT and concepts of PLL/DLL.
• (Jan,14 - May,14) - Teaching Assistant for Intro to VLSI course. Intro to VLSI course involves the concepts of designing of various op-amps, SRAM/DRAM cell using MOSFETS.
• (Aug,14 - Dec,14) - Head Teaching Assistant for Information Theory and Coding course. Information Theory and Coding course involves the concepts of Goals, Block codes and bounds, Repetition Hamming code,Convolution codes, Viterbi hard decision decoding.
• (Jan,15 - May, 15) - Head Teaching Assistant for Error Correcting Codes course. Error correcting codes involves the concepts of construction of block codes and helps in motivation for the convolution of codes.
• (Aug,15 - Dec, 15) - Head Teaching Assistant for Analog & Mixed Signal Design Course. Analog & Mixed Signal Designstarts with the overview of PN Junctions, BJTs and especially MOSFETs. Advance Op-amp designand mixed signal design like DAC, ADC’s and PPL are covered in the later part of the course.
• (Jan, 16 - Dec, 16) - Head Teaching Assistant for VLSI Architectures Course.

Jul 2011 – Aug 2016 · 5 yrs 1 mo

• I have completed my Bachelor of Technology and Master of Science(MS) in field of Asynchronous Processor Architecture. The major areas of interest includes the study of asynchronous handshaking protocols.

May 2013 – Jul 2013 · 2 mos · Hyderabad

• Worked on Linting of EM microprocessor and automated the flow on the Jenkins Server.
• Selected as an only intern to do summer internship at R&D centre of Arc Microprocessors.
• Enhanced the existing rule set of LEDA for Linting and compared it with Spyglass rule set.
• Gained an overview of computer architecture and learnt a new and advanced pipeline.