Anna lakshmi S — Product Engineer
ASIC Design engineer with more than 6 years of experience in verilog RTL design. Skills Experienced in: Micro-Architecture development RTL coding Linting CDC Synthesis Simulation and Debugging Basics of STA UPF Protocols : PCIe, I2C, MIPI_I3C, AMBA-APB, AMBA - AXI RTL related Logic Equivalence Checks Tools Experienced in: Simulation tools : Synopsys VCS,Cadence NC-Sim Linting tools : Novas Lint, Spyglass Lint, Conformal Lint, VC Lint CDC tool : Spyglass CDC, VC CDC Logic Synthesis tools : Design Compiler(DC), RTL Compiler(RC) , Fusion Compiler Low power tools : VCLP Logic Equivalence Check : Conformal FEV
Stackforce AI infers this person is a skilled ASIC Design Engineer with expertise in RTL design and simulation.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 8 mos
Skills
- Asic
- Rtl Design
Career Highlights
- Over 6 years of experience in ASIC design.
- Expertise in Verilog RTL design and simulation.
- Proficient in multiple protocols including PCIe and AMBA.
Work Experience
Intel Corporation
SoC Design Engineer (3 yrs 11 mos)
SpicaWorks
Senior RTL Design Engineer (5 mos)
SmartDV Technologies
RTL Design Engineer (3 yrs 4 mos)
Education
Bachelor's degree at National Engineering College,Kovilpatti
High School at Government Higher Secondary School
