Feb 2022 – Dec 2022 · 10 mos · Hyderabad, Telangana, India

• Working with the Architecture team:
• Adding features in the tool to support timing infrastructure for Architectural changes.
• Developing software tools to bring up and evaluate architectural enhancements.
• Debugging and enhancing placement and routing algorithms for new architectural features.

Dec 2021 – Jan 2022 · 1 mo

Jun 2018 – Dec 2021 · 3 yrs 6 mos

Aug 2017 – Jun 2018 · 10 mos · Noida Area, India

• Backend development for checks on pre synthesis Questa Parse Tree, synthesized Hierarchal/Flattened-Netlist for early detection of potential issues in RTL designs using advanced C++ programming algorithms and data structures
• Added user customizable feature and directive parsing, which suppressed the noisy customer report by up to 20%
• Added flagging mechanism to identify source cause of potential issues which made debugging very easy on this tool
• Lead phase two of the software development stage. Major responsibilities include
• planning and implementing new check rules using advanced C++
• Mentoring new joiners and interns in the team and coordinating with front-end team, quality assurance team for the requirements of R&D team and incorporating their feedback in the tool

Jun 2016 – Jul 2017 · 1 yr 1 mo · Noida Area, India

• Development of EDA tool for detection of potential complex algorithmic and logical issues in RTL designs. Tool flags preliminary synthesis, post-synthesis mismatches, simulation mismatches and suggest potential fixes to the user
• Using Cshell scripting to automate redundant tasks and create RTL designs for running and debugging on the tool
• Completed 70% of all the check rules implemented by the team

May 2015 – Jul 2015 · 2 mos · Noida Area, India

• Received Pre Placement offer.
• Project entitled "Design a solution for automating assertion generation for clock domain crossing protocols using System verilog assertions, coverage and implementing the solution on Mentor's Clock Domain Crossing (CDC) tool".