Venkata Koppu

Software Engineer

Hyderabad, Telangana, India15 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 15 years of experience in verification environments.
Expert in SOC Design Verification and Functional Verification.
Proven track record in tool development and team mentoring.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in EDA tools and methodologies.

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Skills

Core Skills

Soc Design VerificationFunctional VerificationEda/cad Tool Development

Other Skills

IP IntegrationCAD ToolsDFTXilinx VivadoSimulator DevelopmentTapeout MethodologyCoverage Tool DevelopmentAlgorithmsCC++Data StructuresShell ScriptingProgrammingSoftware DevelopmentDesign Patterns

About

With over 15 years of hands-on experience. Worked in various stages of verification environments starting from simulator design to building coverage management tools. Venkata has deep understanding of industry-standard verification methodologies and have successfully applied them to achieve rigorous functional verification goals.

Experience

Amd

Senior Staff Software Engineer

Jan 2021 – Present · 5 yrs 2 mos · Hyderabad, Telangana, India · Hybrid

Design and development of an effective SOC/IP level coverage management tool
Collaborate closely with cross-functional teams, including system architects, design engineers and verification engineers to define verification methodologies and strategies to deliver high quality tapeouts.
Designed and developed coverage tools to enhance coverage closure, resulting in improved quality metrics
Optimized verification environments, reducing time-to-market and increasing productivity
Mentored junior engineers, enabling their growth and enhancing team performance

SOC Design VerificationIP IntegrationFunctional Verification

Nvidia

Senior Software Engineer

Nov 2017 – Jan 2021 · 3 yrs 2 mos · Bengaluru, Karnataka, India

Application Developer
EDA/CAD Tool Development
Involved in the development of core DFT applications used for Nvidia SOC's
Netlist Reading and Tracing
Netlist Auditor Infrastructure
Optimization of applications and algorithms performance

CAD ToolsDFTEDA/CAD Tool Development

Xilinx

Software Engineer

Jul 2012 – May 2017 · 4 yrs 10 mos · Hyderabad

Worked with Interactive Design Tools Team on Compiler Design Techniques, Transformation and Optimizations, Data Graph and Code Generation. Parsing and modeling hardware description language like Verilog and System Verilog applying data structures and algorithms using C, OOP C++, Design Patterns and STL
Worked with FPGA Development and Silicon Technology Team
Bitstream Security of 7 Series FPGA Configuration
Functional verification of Soft IP's such as memory controllers and interfaces for Xilinx FPGA’s which are part of Memory Interface Generator [ Bundled with Vivado and ISE ]

Xilinx VivadoSimulator DevelopmentFunctional Verification