Akash Singh Rawat

Software Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in RTL design engineering.
Expertise in Verilog and SystemVerilog for ASIC development.
Proven track record in cross-functional team collaboration.

Stackforce AI infers this person is a Telecommunications and Semiconductor design engineer with extensive RTL and ASIC expertise.

Contact

Skills

Core Skills

VerilogSystemverilog

Other Skills

CLPSpyglassLintCDCTCLperlVBAMicrocontroller ProgrammingHardware TestingVerificationSilvaco TCADEmbedded SystemsVHDLMatlabFPGA

About

Highly skilled and motivated RTL design engineer with more than 8 years of experience in digital circuit design with specializing in RTL integration and coding. Proficient in industry-standard tools such as VCS, Spyglass CDC and CLP, with a strong track record of delivering high-quality designs on-time. Adept at collaborating with cross-functional teams such as Verification, Implementation and STA teams to ensure project success and possessing a deep understanding of ASIC design methodologies.

Experience

Qualcomm

2 roles

Staff Engineer

Dec 2024 – Present · 1 yr 3 mos

Senior Lead Engineer

Jan 2022 – Nov 2024 · 2 yrs 10 mos

Developing the microarchitecture, integrating the sub blocks and RTL design for Modem Sub System using Verilog/System Verilog.
Running the Lint, CDC and CLP for Modem Sub System.
Supporting MSS verification team for functional and power aware verification.
Supporting and helping SOC/other Sub System teams for their queries related to MSS
Mentoring and helping junior engineers on their queries

VerilogSystemVerilogCLPSpyglassLintCDC

Intel corporation

SoC Design Engineer

May 2019 – Dec 2021 · 2 yrs 7 mos · Bengaluru, Karnataka, India

Currently working as SOC Design Engineer in clocking RTL team where his key responsibilities include
Developing the microarchitecture and RTL design for clocking subsystem using the Verilog/System Verilog.
Doing the functional and sdf validation of the design at unit level.
Running the Lint and CDC for clocking Subsystem
Clocking Subsystem integration in SOC.
Hands on experience with synthesis and LEC tools
Good knowledge of scripting language like TCL, perl and VBA

Tejas networks

Research and Development Engineer

Aug 2016 – May 2019 · 2 yrs 9 mos · Bengaluru Area, India

Verilog Coding for control plane FPGA which includes development of IPs for bus protocols such as I2C, SPI and PMbus
System design, designing product & individual board architecture
Schematics design
Microcontroller Programming
Proto board bring-up, Hardware Troubleshooting
Hardware Testing, Verification
Board Documentation and Test Report Generation
BOM/Lifecycle management