Vishwa Patel — Software Engineer
Stackforce AI infers this person is a DFT Engineer specializing in ASIC design and verification.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 2 mos
Skills
- Dft
- Universal Verification Methodology (uvm)
Career Highlights
- Experienced DFT Engineer with strong skills in UVM.
- Proficient in SystemVerilog and Verilog for verification.
- Solid foundation in ASIC Design and RTL Verification.
Work Experience
MediaTek
DFT Engineer (5 yrs 2 mos)
Maven Silicon
RTL Design and Verification Trainee (3 mos)
RV-VLSI VLSI and Embedded Systems Design Center
RTL Verification trainee (5 mos)
Education
Advanced diploma at RV-VLSI and Embedded Systems Design Center, Bangalore, Karnataka
Bachelor of Engineering at Government Engineering College, Bharuch, Gujarat (GTU)
Science (Physics at BVB's Narmada Vidyalaya, Bharuch, Gujarat
