keerti Goudar

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience
Highly Stable

Key Highlights

  • 5+ years of experience in SOC Design Verification.
  • Expertise in reusable test benches using SV and UVM.
  • Strong background in digital electronics and ASIC verification.
Stackforce AI infers this person is a Design Verification Engineer with a focus on SOC and ASIC technologies.

Contact

Skills

Other Skills

PerforceUniversal Verification Methodology (UVM)SystemVerilogVerilogSVAVerification planDebuggingFunctional VerificationIP verificationGLSSystem on a Chip (SoC)Strategic PlanningC (Programming Language)Microsoft WordMicrosoft Office

About

A competent having 5+ years of experience in SOC Design Verification, can verify the complete design by creating the TB and hooking up the necessary UVC's ,writing the testcases, assertions, adding data integrity checks and analysis the code and functional coverage. ->Good experience in writing Reusable Test benches using SV and UVM. ->Hands on Experience and good understanding on protocols like AHB,APB,SPI,AXI-4. ->Worked on SOC, developed SV and C based test cases. ->Worked on constraint random Verification and Assertion Based Verification using SVA. ->Expertise in Code coverage analysis ,Functional coverage writing and analysis. ->Good knowledge in developing the verification plan and writing the testcases. ->Have good debugging and problem-solving skills. ->Good understanding in Digital Electronics , ASIC verification flow. ->Knowledge in languages like Verilog , C and C++ ->Basic understanding on Perl scripting. * Simulators : Synopsys vcs ,Riviera Pro *Version control Tool : ClearCase, perforce Additional Skill : Basic understanding on neural networks and Facial Recognition algorithms

Experience

Google

Design verification Engineer,Silicon

Oct 2024Present · 1 yr 5 mos · Bangalore Urban, Karnataka, India · Hybrid

Qualcomm

3 roles

Senior Design Verification Engineer

Dec 2023Oct 2024 · 10 mos

  • Working as a part of Wi-Fi - Phy Dv team

Design Verification Engineer

Promoted

Nov 2021Dec 2023 · 2 yrs 1 mo

  • Verification of modem,voice and music chips

Design Verification Engineer(contract)

Nov 2019Nov 2021 · 2 yrs

  • Contract Worked on ultra low power ESL chips

Lancesoft engineering

Design Verification Engineer

Nov 2019Nov 2021 · 2 yrs · Bengaluru, Karnataka, India

Yoctozant technologies private limited

Asic Digital Verification engineer

Jun 2019Nov 2021 · 2 yrs 5 mos · Greater Bengaluru Area

Maven silicon

RTL Design and Verification Trainee/Intern

Jul 2018Jun 2019 · 11 mos · Bengaluru, Karnataka, India

Education

Jain College of Engineering

Bachelor of Engineering - BE — electronics and communication

Jan 2014Jan 2018

Alva's PU

science — PCMB

Jan 2013Jan 2014

S.K.E Society school

High school — 10

Jan 2011Jan 2012

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