Subhashis Das 🇮🇳

Software Engineer

Bengaluru, Karnataka, India6 yrs 5 mos experience

Key Highlights

Expertise in Physical Design and STA for high-performance ICs.
Proficient in digital and analog hardware design.
Strong leadership skills demonstrated through student body roles.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Physical Design and Hardware Engineering.

Contact

Skills

Core Skills

Physical DesignDigital Hardware Design

Other Skills

STAPlacement (PNR)Clock Tree SynthesisTcl-TkPNRTime ManagementTeam LeadershipTechnological InnovationPublic RelationsEvent ManagementMaintenance ManagementTeamworkPViremShell Scripting

About

I am a dedicated, smart working individual having acquired knowledge in digital and analog hardware including hardware design. I am a fresh Btech graduate of IITG with a decent grade point. I have worked as an intern at Qualcomm during 2021 and hoping to continue being an asset to the organization. I have been involved in memristor research, 5G/6G communications, ML/AI, and Verilog/VHDL projects. I am also slightly proficient in coding especially in languages C/C++ and python with good strength in Matlab, Verilog, Spice, and Linux environments. I have also been involved with student body positions at various levels honing my skills in management and the overall welfare of society through various voluntary works. Hardware Profile| Engineer | Researcher

Experience

6 yrs 5 mos

Total Experience

2 yrs 7 mos

Average Tenure

1 yr 2 mos

Current Experience

Broadcom

ASIC Physical Design Engineer

Feb 2025 – Present · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Physical DesignSTA

Qualcomm

3 roles

Physical Design Engineer

Promoted

Dec 2023 – Feb 2025 · 1 yr 2 mos · Hyderabad, Telangana, India

I am involved with floorplan, PNR, and STA activities for high-performance, low-power designs. I take care of floorplan (including PDN, PV checks) and PNR tasks (Placement, Clock Tree synthesis, Spine building, Routing) for high-performance designs (Frequency > 3 GHz) with instance count > 2 Mil.

Placement (PNR)Clock Tree SynthesisPhysical Design

Associate Engineer

Jul 2022 – Dec 2023 · 1 yr 5 mos · Hyderabad, Telangana, India

First job starting as part of the Physical Design (PD) team in Engineering division of Qualcomm India. I have supported CPU-SOC interface wrapper design and SOC blocks.

Tcl-TkPNRPhysical Design