Kanika Juneja

DevOps Engineer

Delhi, India6 yrs 8 mos experience

Key Highlights

Expert in formal verification with extensive tool experience.
Led verification for AI-focused semiconductor projects.
Strong mentoring skills for junior engineers.

Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on formal verification methodologies.

Contact

Skills

Core Skills

Formal Verification

Other Skills

Formal Verification Sign-offMentoring freshersFPVCOV/FCAUNRSEQ/SECCONN appsRTL DesignSGLINT appSystem Verilog AssertionsQuestaSimAnalog electronicsCMOSDesign Rule Checking (DRC)Layout Versus Schematic (LVS)

About

Experience in Formal Verification with expertise in System Verilog Assertions and Formal Property Verification using JasperGold and VC Formal tool. Experienced in formally verifying- 1. AMD: MI450 SoC(AI HARDWARE) : Training, Inference & HPC for data centres. 2. Intel: QAT : Accelerator. 3. Cadence: AMBA protocols-AHB,AXI For details, refer to Experience section. Full of zest for life, technically well versed, good communication skills and loves challenges.

Experience

6 yrs 8 mos

Total Experience

2 yrs 1 mo

Average Tenure

3 mos

Current Experience

Qualcomm

Senior Lead Formal Verification Engineer

Jan 2026 – Present · 3 mos · Bangalore · On-site

GPU Formal Verification

Amd

Sr. Silicon Design Engineer

Aug 2023 – Jan 2026 · 2 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Worked in GPU(GFX) formal verification team.
Formally signed-off blocks in upcoming MI450 SoC which is designed for AI Training, Inference and HPC workloads in data centres.
Blocks: Cache memory management sub system
Expertise: FPV, COV/FCA, UNR, SEQ/SEC, CONN apps

Formal Verification Sign-offMentoring freshersFormal Verification

Intel corporation

Pre-Silicon Verification Engineer

Apr 2022 – Aug 2023 · 1 yr 4 mos · Bengaluru, Karnataka, India

Worked as a Formal verification engineer in Quick Assist Technology(QAT)- Accelerator team, Intel.
Created FPV SVA files from scratch.
FPV enablement for various modules and models.
Warning analysis (waiver, fix) using SGLINT app.
Exposure of : CONN, SEC, XPROP apps.
RTL Design of a few modules written from scratch.

RTL DesignFormal Verification

Cadence design systems

2 roles

Software Engineer II

Jul 2020 – Apr 2022 · 1 yr 9 mos

Worked as a Formal Verification Engineer, Assertion based Verification IP(ABVIP) team.
Developed and tested ABVIPs using Formal property verification app of JasperGold tool.
Created properties for new features of latest AXI/ACE5-H.
Maintanence of legacy code.
Resolved customer issues.
Protocols worked on- OCP, AHB, AXI.

System Verilog AssertionsFormal Verification