Kartik Bhardwaj

Software Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience

Key Highlights

  • Expert in high-speed SerDes design across advanced nodes
  • Proficient in full design flow from specification to tape-out
  • Strong academic background with GATE ECE Scholar recognition
Stackforce AI infers this person is a Semiconductor Design Engineer specializing in Analog and Mixed-Signal IC design.

Contact

Skills

Core Skills

Analog Integrated Circuit DesignMixed-signal Ic DesignSerdesProject ManagementLeadership

Other Skills

Cadence VirtuosoAnalog Circuit DesignTransistorsCadence SpectreGPIOAnalog CircuitsVirtuosoSpectreOpampAnalytical Skillsanalog & mixed signal DesignAnalog SemiconductorsAdvance digital CircuitsProblem SolvingDigital Logic

About

I design analog and mixed-signal circuits that work on silicon — not just in simulation. Around 5 years in the semiconductor industry, with deep specialization in high-speed SerDes design across TSMC 3nm FinFET, TSMC N2 GAAFET, and Samsung 4nm process nodes. My work spans the full design flow — from specification and schematic to post-layout verification and tape-out readiness. Technical focus areas: → SerDes signal chain: Signal detection, RX termination, CMUX, Clock distribution, LVDS interface,GPIO, standard cell characterization → Simulation: DC, AC, Transient, Stability, Jitter, Monte Carlo, Corner analysis → Post-layout: LPE extraction, parasitic-aware analysis, Paragon-X correlation → Standards: PCIe , USB , UFS, GMII, 10Gbps+ SerDes Tools: Cadence Virtuoso, Spectre, ADE-XL, Explorer, Assembler, Paragon-X Currently working on high-speed SerDes design blocks at advanced FinFET nodes for leading semiconductor client engagements. M.Tech in VLSI Design — 97.3% Honours | GATE ECE Scholar | All India Rank 13 (BEL Exam) Open to connecting with engineers, founders, and teams working in high-speed analog, mixed-signal, and SerDes design.

Experience

Tech mahindra

Senior Analog Design Engineer (Client: Qualcomm)

Nov 2024Present · 1 yr 5 mos · India · On-site

  • ✅ Pre and post-layout simulations to validate signal-detection thresholds at TSMC 3nm (N3e) FinFET
  • ✅ Corner & Monte Carlo analysis across full PVT range
  • ✅ Parasitic extraction and analysis using Paragon-X
  • ✅ Tape-out readiness review for analog schematics
Analog Integrated Circuit DesignSerDesCadence VirtuosoAnalog Circuit DesignMixed-Signal IC Design

Aryavarta circuits private limited

Circuit Design Engineer (Client: AMD)

Feb 2024Oct 2024 · 8 mos · Banglore · On-site

TransistorsAnalog Integrated Circuit DesignCadence SpectreGPIOAnalog CircuitsVirtuoso+3

Indian railways

Senior Technical Associate

Oct 2023Feb 2024 · 4 mos · India · On-site

  • Electronics domain technical role while transitioning back to semiconductor industry

Career break

Professional development

Jan 2021Sep 2023 · 2 yrs 8 mos · Madhya Pradesh, India

  • M.Tech — Full Time (GATE Scholar)

Bharat electronics limited

2 roles

Project Engineer

Apr 2020Jan 2021 · 9 mos

Project ManagementTransistorsAnalytical Skillsanalog & mixed signal DesignAnalog SemiconductorsCadence Virtuoso+3

Deputy Engineer ( R&D)

Apr 2018Apr 2020 · 2 yrs

Transistorsanalog & mixed signal DesignAnalog Circuit DesignOpampAnalog Integrated Circuit Design

Unacademy

GATE / ESE faculty ( ELECTRONICS)

Sep 2017Jan 2020 · 2 yrs 4 mos · Banglore

  • ✅Prepare content for All India level exam like GATE/ESE
  • ✅Educate about the concepts of Advance Digital CIrcuits and anlog devices
  • ➕MORE FACTS
  • ✅20k + followers
  • ✅ 1000+ free lessons
LeadershipTransistorsProblem SolvingAnalytical Skillsanalog & mixed signal DesignDigital Logic+9

Education

Rajiv Gandhi Prodyogiki Vishwavidyalaya

Master of Technology - MTech — VLSI Design

Jan 2021Jul 2023

Dr. A.P.J. Abdul Kalam Technical University

Bachelor's degree

Jan 2010Jan 2014

Kendriya Vidyalaya

High School/Secondary Certificate Programs

Jan 2001Jan 2010

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