Alexandro Giron

Director of Engineering

Zapopan, Jalisco, Mexico25 yrs 5 mos experience

Highly Stable

Key Highlights

Over 20 years of experience in semiconductor design.
Proven track record in leading high-level engineering teams.
Expertise in developing custom verification methodologies.

Stackforce AI infers this person is a semiconductor engineering expert with extensive leadership experience.

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Skills

Core Skills

Mixed Signal Design And VerificationDigital DesignVerification Methodologies

Other Skills

ASICAcademic WritingAnalogAnalog Circuit DesignBehavioral ModelingCMOSCadenceCadence SpectreCadence VirtuosoDebuggingDigital IC DesignElectronicsEmployee TrainingFPGAFormal Verification

About

I am looking to grow or create research and development teams focused on semiconductor or electronics areas and make them successful. I apply all my leadership, empowerment, academic and +20 years of industrial experience to manage high level teams. I got a Master degree on Integrated Circuit Design at INAOE Mexico in 2003. Worked for Freescale Semiconductor as Design Engineer from 2004 to 2005. During 2005-2006 worked for Crouzet Mexicana. (Schneider Electric) as a Senior Engineer in charge of the electronic design of solid state relays and power circuits. In 2006 returned to Freescale Semiconductor Guadalajara to continue with the integrated circuit design. After collaborating as Analog Designer I started a Digital Design and Verification area in Mexico. In 2015 joined Intel as Sr. Pre-silicon Verification Engineer. I took the role of Engineering Manager since 2017. Besides my industry experience I have been professor for around 14 years, at the Universidad Iberoamericana Puebla From 2001 to 2006 and at the ITESO in Guadalajara from 2007 to 2016. I got a PhD in Egineering Sciences in 2021 at ITESO University.

Experience

Micron technology

Director of High Bandwidth Memory (HBM) Engineering

Oct 2025 – Present · 5 mos · Tlaquepaque, Jalisco, Mexico · On-site

Intel corporation

2 roles

Engineering Manager (Pre-Silicon Validation)

Promoted

Dec 2017 – Oct 2025 · 7 yrs 10 mos

Sr. Pre-Silicon Validation Egineer

Nov 2015 – Nov 2017 · 2 yrs

Iteso

Professor

Oct 2007 – Dec 2016 · 9 yrs 2 mos · Guadalajara Area, Mexico

Professor.
Member of the academic team of the EDCI (Especialdad en Diseno de Circuitos Integrados)

Freescale semiconductor

Mixed signal Design and Verification Technical Leader

Dec 2006 – Oct 2015 · 8 yrs 10 mos · Guadalajara Area, Mexico

7 Years leading, planning and coordinating the activities of the Digital Design and Verification team in Mexico.
2 years leading and coordinating Freescale Mexico innovation and patent efforts.
Experience working with Jalisco government in activities related with innovation an patent programs
Member of Freescale Mexico synergy groups like GPTW, Innovation and supporting company fundamentals.
8 patent disclosures issued inside the company achieving one Trade Secret and a Patent Filing.
1 patent filed in Mexico.
Technical Experience:
Worked with 90nm, 45nm, 28nm and 16nm technologies.
Focused on the Creation of Custom Verification Methodologies as well as on the verification quality improvement (verification holes detection and bug reduction).
Execution and coordination of verification methodologies and activities such as:
RTL Verification, test bench, debug, Back annotated Gate level verification, Code coverage.
Functional coverage. Cross domain clock analysis. Static timing Analysis. AMS verification.