Sep 2024 – Dec 2025 · 1 yr 3 mos · Bengaluru, Karnataka, India · Remote

Apr 2024 – Aug 2024 · 4 mos · Bengaluru, Karnataka, India · On-site

Jan 2022 – Mar 2024 · 2 yrs 2 mos · Hyderabad, Telangana, India

• Linux capable Multi-threaded RISC-V Core - RV64GCBHSU **
• Led the team in the design & development of an RV64GCBHSU core an in-order, dual-issue, early-late ALU pipeline with features such as sophisticated branch prediction, RAS, Store Buffer, etc. Standard RISCV ISA features such as PMP, PMA, HPM, along with CMO & Sstc extensions were also implemented. The Level-1 Instruction & Data Caches and MMU were all designed for multi-threaded architecture. Operating Systems such as Linux, FreeRToS and BAO Hypervisor were booted up on FPGA Environment.
• A complete support for Split-Lock FuSa-DCLS configuration was added. FMEA/FMEDA analysis was performed for DCLS core on VC-FSM; fault simulations were performed to calculate diagnostic coverage on VC-ZOIX. Floor-planned blocks & collaborated with the Physical Design team to implement Structured Data Path for Register Files and micro-TLBs.
• Incorporated efficient project management, version control, and documentation practices to develop & maintain a high-quality code base that makes extensive use of advanced System Verilog features, parametrization and is made generic to aid in developing other flavors of the RISC-V core with minimum effort. The IP code base was developed as tech node agnostic; maintained for TSMC 5nm & 16nm.
• Invested significant efforts in parallelizing & automating routine and mundane tasks such as lints, synthesis, and regressions. Developed generic scripts so that once setup, the tool flow didn't need to be set up anew for different IPs.

Dec 2020 – Dec 2021 · 1 yr · Hyderabad, Telangana, India

• Sv39 & Sv39x4 Memory Management Unit **
• Responsible for the design of RISC-V SV39 & SV39x4 compliant MMU for multi-threaded core, implemented architectural features to reduce the TLB miss rate, PTW latency, critical path, & power consumption. SvNAPOT and SvPBMT extensions were implemented in compliance with RISC-V specifications. The TLB lookup and Virtual Memory check logic was architected to accommodate AGU unit to improve performance and operating frequency.
• Unified-TLB was implemented along with micro-TLB to improve TLB reach. Architectural features to effectively utilize the Unified-TLB memories, reduce power & PTW latency were implemented. g-TLB (pointer cache) was implemented in Sv39x4 MMU to further reduce the 2D-PTW latency.
• Developed RTL source code with various configurations such as parametrized size of micro TLBs, multiple replacement policies, etc. The code structures were defined such as implementing an Sv48/Sv57 policy would require little effort.

Sep 2018 – Dec 2020 · 2 yrs 3 mos · Banglore

• L1 Instruction Cache **
• Responsible for Design and Development of Level-1 Instruction Cache for an Out-of-Order Super-scalar RISC-V Processor with the goal of implementing architectural features to reduce the Average Memory access time.
• Developed the RTL source code with various configurations such as Replacement Policies, Victim Cache Size & it's Replacement Policy, and Enabling Pre-Fetchers etc. Integrated Snoop Functionality in Level-1 Instruction Cache for multi-core environment. Validated the design by porting it on FPGA (VCU118 Ultrascale+) along synthesizable Test environment developed in Bluespec.

Jun 2016 – Jun 2016 · 0 mo · Udaipur Area, India

• STUDY OF COMMUNICATION, NAVIGATION AND SURVELLIANCE

Jun 2015 – Jul 2015 · 1 mo · Udaipur Area, India

• Basic Level Vocational Training