Anurag Singh

Software Engineer

Budapest, Budapest, Hungary6 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Low Power Design and Microarchitecture.
Proven experience in MMU and GIC architecture.
Strong background in RTL Design and Debug Infrastructure.

Stackforce AI infers this person is a highly skilled ASIC Design Engineer specializing in Low Power and Microarchitecture design.

Contact

anuragsi003@gmail.com LinkedIn

Skills

Core Skills

Mmu DesignLow Power DesignIp DesignMicroarchitecture Design

Other Skills

RTL DesignArchitectural DesignLogic SynthesisDebug InfrastructureAMBA ProtocolsMMU ArchitectureGICCPU designHardware DesignHardware DevelopmentInterrupt ControllerRISC-VLOW Power ControllersApplication-Specific Integrated Circuits (ASIC)Resource power management

About

Senior IP Design Engineer at ARM. Microarchitecture design, Debug, MMU, GIC, Low Power Design. RISC-V CPU

Experience

Arm

Senior Design Engineer

Jun 2024 – Present · 1 yr 9 mos · Budapest, Hungary · On-site

MMU Design
(Address Translation , caching & Security)

RTL DesignArchitectural DesignMMU DesignLow Power Design

Qualcomm

Senior Design Engineer

Jul 2019 – Jun 2024 · 4 yrs 11 mos · Bengaluru, Karnataka, India

1. IP Design/RTL Design/Microarchitecture Design.
2. Low Power Design: Designing the intelligent clock-gating and power gating IP for SOC infrastructure. Have in-depth understanding of SOC power infrastructure: Power rails, Voltages corners, DCVS/RFAS Implementation , Clock-Controllers, PMIC
3. Debug Infrastructure, AMBA Protocols, ARM SOC-400 Architecture, CDC-Lint-STA-DFT Checks.
4. MMU Architecture, Caching, Virtualization and Security.
5. GIC(Interrupt controller):Interrupt Routing, prioritisation and Grouping. Virtual interruption handling.
6. Formal Verification: Model Development for Data-Path Verification: CDC components & FTB(MMU).

RTL DesignLogic SynthesisLow Power DesignDebug InfrastructureAMBA ProtocolsMMU Architecture+3