Sachin K.

Software Engineer

Pune, Maharashtra, India4 yrs 9 mos experience

Highly Stable

Key Highlights

Expertise in VLSI Physical Design and Implementation.
Successful tapeouts in deep submicron technology.
Proficient in industry-standard design tools and methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

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Skills

Core Skills

Physical DesignVlsiResearch

Other Skills

SynthesisLECPnRSTAIR/EM AnalysisFloor-planPhysical ImplementationPower-planPlacementCTSTiming ClosureRoutingExtractionPhysical VerificationCrosstalk Analysis

About

Technology Node:- Samsung 4nm, TSMC 3nm, 5nm, 6nm, 7nm, 16nm and 28nm. • Having physical design experience, with recent successful tapeouts in deep submicron technology. • Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Work closely in the Design Implementation team for physical design, physical verification & power related activities across various SoCs. • Work on Floor planning, power planning, P&R, CTS, timing closure, IR analysis, and formal equivalence for block level, full chip hierarchical, and flat designs • Work on creating setup and scripts for DRC, LVS, Antenna, and density checks, report generation, analysis, debug, and implementing the fixes in the physical design database • Assist in full chip physical design activities like bumping and RDL routing • Interface with full chip level engineers for chip finishing tasks such as LVS, DRC, Antenna check, etc • Work experienced in industry standard tools, understand their capabilities and underlying algorithms.

Experience

4 yrs 9 mos

Total Experience

2 yrs 2 mos

Average Tenure

4 mos

Current Experience

Qualcomm

Technical Professional

Dec 2025 – Present · 4 mos · Pune, Maharashtra, India · Hybrid

Alphawave semi

Engineer II - VLSI

Oct 2024 – Dec 2025 · 1 yr 2 mos · Pune · Hybrid

Keenheads

Design Engineer

Jul 2021 – Oct 2024 · 3 yrs 3 mos · Noida, Uttar Pradesh, India · On-site

Synthesis, LEC, PnR, STA and IR/EM Analysis
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Work with the Front-end teams to update and tune timing constraints.
Directly responsible for the physical design and implementation (from netlist to GDSII tape-out) of design partition(s) with high frequencies for a highly complex soc utilizing state of the art process technology. Ensure that partition(s) deliverable and design quality as per schedule and design parameters.
Validate the design for functional and electrical robustness.
Helped peer members to resolves their issues related to PnR.

SynthesisLECPnRSTAIR/EM AnalysisFloor-plan+12

Vlsiguru training institute

Physical Design

Feb 2021 – Jul 2021 · 5 mos · Bengaluru, Karnataka, India · Remote

• Get in-depth knowledge of all aspects of physical design flow from Netlist to GDSII including Floorplaning, Power Planning, Placement, Routing, Clock Tree Synthesis, Static Timing Analysis, Power Analysis and ECO.

Static Timing AnalysisPhysical Design

Indian institute of technology, patna

Research Intern

May 2018 – Jul 2018 · 2 mos · India · On-site

In this research work two Micro-Electro-Mechanical System (MEMS) capacitive pressure sensors with different dielectric are designed and simulated with device simulation software. I have investigated the different performance parameters for MEMS capacitive pressure sensor, such as the total displacement, capacitance, sensitivity etc. for the optimal design of pressure sensor.

ResearchCOMSOL