Dinesh Devaraconda — Product Engineer
Familiar with EDA Tools like : - RTL Compiler- Logic Synthesis . - Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis - Encounter Timing System –Static Timing Analysis and Crosstalk Analysis
Stackforce AI infers this person is a VLSI Design Engineer with expertise in memory design and EDA tools.
Location: Hyderabad, Telangana, India
Experience: 11 yrs 9 mos
Skills
- Sram
- Digital Designs
Career Highlights
- Experienced Memory Design Engineer at Intel Corporation.
- Proficient in EDA tools and static timing analysis.
- Strong background in SRAM and digital design methodologies.
Work Experience
Intel Corporation
Memory Design Engineer (8 yrs 6 mos)
ARM
Design Engineer (1 yr 5 mos)
VIT UNIVERSITY
MTECH- VLSI DESIGN (1 yr 10 mos)
Education
Master of Technology (MTech) at VIT UNIVERSITY
Bachelor of Technology (BTech) at cvr college of engineering
at Defence Labs School, Kanchanbagh
at Defence Labs School, Kanchanbagh
