Harinadha Reddy Bodasani — DevOps Engineer
Senior Design Engineer at Alphawave Semi. Below are my Skills: > Hands-on RTL design engineer with 7 years of strong RTL design, micro-architecture, and implementation experience over multiple IP development projects > Strong knowledge in ASIC and FPGA logic synthesis, Timing Analysis, and Timing closure > Hands-on experience in Spyglass-LINT, Spyglass-CDC, and Design Compiler(DC) > Familiarity with Multiple simulators (Verdi, simvision, Vivado, Modelsim, Verdi, and Cadence Xcelium) > Basic knowledge of bus architectures like APB, AHB, and AXI > IP Development Experience in Gigabit Ethernet > IP Development experience in ARM System-MMU subsystem > Good understanding of UCIE > Basic knowledge of Interlaken IP > Basic programming skill in Perl
Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in RTL design and verification.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Rtl Design
- Logic Synthesis
- Digital Design
- Verification
Career Highlights
- 7 years of hands-on RTL design experience.
- Expertise in ASIC and FPGA logic synthesis.
- Proficient in multiple design and verification tools.
Work Experience
Qualcomm
Technical Professional (4 mos)
Alphawave Semi
Senior IP Design Engineer 2 (8 mos)
Senior Engineer (2 yrs 8 mos)
Cientra
RTL DESIGN ENGINEER (3 yrs 3 mos)
Maven Silicon
VLSI DESIGN Intern (11 mos)
Education
BTech - Bachelor of Technology at Aditya College of Engineering, Madanapalle
