Naveen K. — Software Engineer

• Over 10+ years of experience in ASIC/ FPGA flows and methodologies for design and verification at IP/subsystem/SoC level. • Adept at verifying ASICs using SystemVerilog as well as in Coverage Driven verification Methodology. • Fluency with Verilog, SystemVerilog and OVM/UVM methodologies,assertion based verification. • Experience in developing a thorough test plan, Strong ability to analyze specifications to identify the test scenarios needed to achieve functional testing and coverage goals. • Expert in creating object-oriented, self-checking, reusable test benches for block-level testing and full-chip simulation with constrained-random stimulus and coverage analysis. • Quick at finding, debugging, and analyzing the bugs/failures in RTL and fixing them. • Several project cycles from concept through complete release. • Possess Sound Analytical, Quantitative Research and Problem-Solving Skills with rich experience in Verification Methodologies.

Stackforce AI infers this person is a highly skilled ASIC/FPGA verification engineer with extensive experience in VLSI design.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 1 mo