Er. Anoushka Tripathi ā Co-Founder
š Namaskaram! Iām Anoushka Tripathi, a passionate VLSI engineer blending cutting-edge semiconductor technology with Bharatiya heritage. I recently graduated from Shri Ramdeobaba College of Engineering and Management and am now stepping into my professional journey as a Full-Time VLSI Engineer at Monk Tech, where I will be contributing to fabrication and VLSI design projects that support Indiaās growing semiconductor ecosystem. š¬ During my internship at SSPL DRDO, Ministry of Defence, I worked on an FPGA-based Peak Detection System for real-time signal processing in defense applications. This project was a proud contribution to Make in Bharat, aligning with national goals for self-reliant tech innovation. š I secured 2nd position at the DIR-V Symposium Hackathon, where my team designed an FPGA-based Systolic Array, significantly boosting performance in GEMM operationsāa key workload in AI and DSP systems. š” As the Founder of Aryavartasemi Community, I lead a community focused on educational content in VLSI, chip design, and semiconductor technologies. We host workshops, webinars, and industry expert sessions, fostering collaboration among aspiring engineers and seasoned professionals to strengthen Indiaās semiconductor landscape. š§ Technical Expertise: RISC-V Design & Verification FPGA-based Digital Systems Digital Circuit Design using Verilog & C++ Vivado, Microchip & Open Source EDA Tools UVM-based Verification (UART, AXI, APB) š± Iām enthusiastic about solving complex hardware design problems and collaborating on innovations that fuel Indiaās chip design revolution.
Stackforce AI infers this person is a VLSI engineer with a focus on semiconductor technology and defense applications.
Location: Gurugram, Haryana, India
Experience: 9 mos
Skills
- Universal Verification Methodology (uvm)
- Risc-v Design & Verification
- Analog Circuit Design
- Industrial Robotics
Career Highlights
- Contributed to defense tech with FPGA-based systems.
- Led community initiatives in VLSI education.
- Achieved 2nd place in a prestigious hackathon.
Work Experience
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Design Verification Engineer (1 mo)
RISC-V INDIAN DEVELOPERS FORUM
Technology Ambassador (1 mo)
Aryavartasemi
Founder (5 mos)
Monk Tech Private Limited
Design Verification Engineer (8 mos)
DRDO, Ministry of Defence, Govt. of India
FPGA Trainee (5 mos)
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Verification intern (2 mos)
VLSI System Design
Hardware Intern & Teaching Assistant (1 mo)
iDEX - DIO
Defence Acceleration Intern (1 mo)
La Fondation Dassault SystĆØmes
ConnectNext Intern (2 mos)
Tata Technologies
Intern (1 mo)
Education
Bachelor of Technology - BTech at Shri Ramdeobaba College of Engineering and Management
Class 11 & 12 at Central Board of Secondary Education
Class 10 at Bharatiya Vidya Bhavan's
