Arunit Raj

Software Engineer

Patna, Bihar, India2 yrs 6 mos experience

Highly Stable

Key Highlights

Expertise in power aware verification for SoC designs.
Strong background in VLSI design and ASIC development.
Proficient in RTL design and functional verification methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC development.

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Skills

Core Skills

Functional VerificationRtl DesignAsic

Other Skills

UPFVerilog hdlApplication-Specific Integrated Circuits (ASIC)Logic DesignElectrical EngineeringDigital DesignsProblem SolvingDesignEngineeringUniversal Verification Methodology (UVM)SystemVerilogAnalog Circuit DesignCMOS VLSI designLTSpiceProject Management

Experience

2 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 6 mos

Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Apr 2026 – Present · 0 mo · Hyderabad

Silicon Design Engineer 2

Sep 2023 – Mar 2026 · 2 yrs 6 mos · Hyderabad

Part of Power Verification team for SoC design.

UPFVerilog hdlFunctional VerificationRTL Design

Smartsoc solutions pvt ltd

Design Engineer 1

Jun 2023 – Aug 2023 · 2 mos · Hyderabad, Telangana, India · On-site

Amd

Co-op Intern

Jul 2022 – Jan 2023 · 6 mos · Hyderabad, Telangana, India · On-site

Low Power Team - performs power aware verification for different IP's in SoC •••
Creating and maintaining regression test suites for different IP's present in a SoC
Debugging build generated and simulation generated files for each test case
Understood the generic architecture AMD uses for the execution and verification
of various IP blocks
Learnt how to apply low power techniques like Multi-Vdd, Clock Gating, Power Gating to any design
Perform RTL modeling and test bench (also written UPF for correct PG Entry-Exit) for implementing
above techniques in a SoC prototype
USB IP owner for one of the undergoing project
Writing test plans and handled all the errors for that specific IP.
Used VCS tool for debugging purpose