Gokul B

Intern

Bengaluru, Karnataka, India0 mo experience

Key Highlights

  • Hands-on experience in Post-Silicon Validation.
  • Proficient in RTL Design with Verilog and SystemVerilog.
  • Strong understanding of high-speed interfaces like UCIe.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in VLSI design and post-silicon validation.

Contact

Skills

Core Skills

Post-silicon ValidationHigh-speed InterfacesRtl Design

Other Skills

UCIeEye Diagram AnalysisSilicon bringupPI CalibrationPythonLinuxProblem SolvingVerilogI2CShell ScriptingDebuggingDigital Design & Timing ConceptsCommunication ProtocolsCustomer SatisfactionReal-Time Operating Systems (RTOS)

About

VLSI-focused ECE graduate with hands-on experience in Post-Silicon Validation and RTL Design. Currently working as a Post-Silicon Validation Intern at Alphawave Semi on high-speed interconnect validation (UCIe), where I work with silicon bring-up, register-level debugging, PI calibration, eye monitoring, and error analysis. Previously completed an RTL Design internship focusing on Verilog-based digital blocks and protocol-level understanding. Core skills: • Post-Silicon Validation & Debug • High-Speed Interfaces: uCIE • RTL Design: Verilog, SystemVerilog • Digital Design & Timing Concepts • Protocols: I2C • Linux, scripting, register-level access Looking for full-time opportunities in: Post-Silicon Validation / RTL Design / Digital VLSI roles.

Experience

0 mo
Total Experience
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Average Tenure
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Current Experience

Alphawave semi

Post-Silicon Validation Intern

Jul 2025Present · 10 mos · Bengaluru, Karnataka, India · On-site

  • Performed post-silicon validation of high-speed uCIE interfaces
  • Involved in silicon bring-up, register-level debug, and PI calibration
  • Analyzed eye diagrams, BER, and error counters for link health
  • Worked closely with RTL, firmware, and architecture teams to debug issues
  • Used Python-based validation frameworks and Linux environments
UCIeEye Diagram AnalysisSilicon bringupPI CalibrationPythonLinux+2

Schneider electric

Intern

Jan 2025Jul 2025 · 6 mos · Bengaluru, Karnataka, India · On-site

Proxelera

VLSI Design

Sep 2024Dec 2024 · 3 mos · Mysore, Karnataka, India · On-site

  • Designed and verified digital blocks using Verilog
  • Implemented and tested I2C protocol at RTL level
  • Developed testbenches and performed functional verification
  • Gained strong understanding of FSMs, timing, and digital design flow
LinuxProblem SolvingRTL Design

Education

Vidya Vardhaka College of Engineering, MYSORE

Bachelor of Engineering - BE

Jan 2021Sep 2025

Vijaya vittala composite pu college

PCMB

Jun 2018Jun 2020

JSS Public School

Jun 2006Apr 2018

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