Ajay Rupanagudi

Engineering Manager

Bengaluru, Karnataka, India14 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Hands-on expertise in ASIC design and verification.
Awarded for contributions to PCIe Advanced Debug Feature.
Proficient in multiple hardware description languages.

Stackforce AI infers this person is a Semiconductor Verification Engineer with strong ASIC and PCIe expertise.

Contact

Skills

Core Skills

VerificationPci Express

Other Skills

Test bench developmentScoreboards for VerificationLow Power testingCommon Power Format (CPF)Palladium XPPost silicon ValidationMatlabCMicrosoft OfficeMicrosoft ExcelPhotoshopXilinxModelSimAltera QuartusFPGA

About

-Hands On knowledge of System Verilog , Specman E , Verilog and VHDL languages and verification techniques. -Expertise in PCIe ,Nvlink ,PIPE, APB and AXI protocols -Good understanding of the ASIC design flow. -Strong debugging and logic analysis on system level issues -Experience in developing testbench using verification methodologies (UVM) -Experience of writing testcases for verification and SOC integration -Proficient in scripting with PERL . -Employee Spot Light Award by Product Manager for my contribution on PCIe Advance Debug Feature -Background in Digital Logic Design and Verification.

Experience

14 yrs 11 mos

Total Experience

3 yrs 9 mos

Average Tenure

10 yrs

Current Experience

Nvidia

2 roles

Engineering Manager

Promoted

Apr 2024 – Present · 2 yrs 1 mo

Senior ASIC Engineer

May 2016 – Apr 2024 · 7 yrs 11 mos

Pmc-sierra

2 roles

Product Verification Engineer Level 2

Promoted

May 2014 – May 2016 · 2 yrs

Responsible for development of reusable Test bench and Scoreboards for Verification of Physical layer of the PCI Express Gen3 Design , Low Power testing using Common Power Format (CPF) tools, Supporting Palladium XP and Post silicon Validation Teams,

Test bench developmentScoreboards for VerificationLow Power testingCommon Power Format (CPF)Palladium XPPost silicon Validation+2

Product Verification Engineer Level 1

Jun 2012 – May 2014 · 1 yr 11 mos

Responsible for development of reusable Test bench and Scoreboards for Verification of Physical layer of the PCI Express Gen3 Design , Low Power testing using Common Power Format (CPF) tools, Supporting Palladium XP and Post silicon Validation Teams,

Test bench developmentScoreboards for VerificationLow Power testingCommon Power Format (CPF)Palladium XPPost silicon Validation+2

National institute of technology tiruchirappalli

Research Student

Jan 2012 – May 2012 · 4 mos

Project on "Developing a reliable Network interface for Network on chip applications "

Pragyan (international techno-management fest, nit trichy)

Head ,Workshops

May 2011 – May 2012 · 1 yr

As the head of Workshops was responsible for associating with different organizations in conducting technical workshops . I Supervised a team of 30 people in conducting 6 workshops . The role involved people management and Decision making