Rohit Mundada

Product Engineer

Pune, Maharashtra, India8 yrs 3 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

7+ years of experience in semiconductor design.
Expert in functional safety and design verification.
Awarded Best Outgoing Student in college.

Stackforce AI infers this person is a Semiconductor Design Verification Expert with a focus on functional safety.

Contact

Skills

Core Skills

Functional SafetyDesign VerificationSoc IntegrationEthernet Verification

Other Skills

DCLSMemory Management UnitInterrupt ArchitectureSystem on a Chip (SoC)AXIEthernetUniversal Verification Methodology (UVM)IP VerificationRISC-VXtensaIPXACTHardware Safety MechanismSoftware Safety MechanismSoftware Test LibrariesAssembly Language

About

A true tech nerd with 7+ years of work experience in semiconductor industry and M.Tech. in Micro-electronics. 👨🏻‍💻Which means I can talk your ear off about processors, computer architecture, or any kind of chip you can think of. But I’m not all work and no play - I was awarded as Best Outgoing Student in college and well I’m always for a good laugh. So when I’m not tinkering with circuits though, you’ll find me with a backpack on a trail, trying latest restaurants, in a cafe with a book or on a couch with gaming controller in hand. 🏝️ Let’s connect and share stories about our favourite things - tech or otherwise 👓

Experience

8 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

5 yrs 5 mos

Current Experience

Cadence

3 roles

Principal Design Engineer

Promoted

Jan 2026 – Present · 3 mos · On-site

Lead Design Engineer

Promoted

Jul 2023 – Present · 2 yrs 9 mos · On-site

Lead the Functional Safety effort for Xtensa processors, driving the design and delivery of the Dual Core Lockstep (DCLS) module to enable ASIL-B and ASIL-D capable configurations for safety‑critical automotive and embedded applications. Own key memory‑related safety features, including definition and implementation of hardware and software safety mechanisms for robust detection and handling of random memory faults in line with ISO 26262.
Play a core role in achieving functional safety certification by aligning architecture, implementation, and verification with ASIL-B and ASIL-D requirements, focusing on diagnostic coverage, redundancy, and fault tolerance across the processor subsystem. Collaborate closely with cross‑functional RTL, verification, and software teams to translate safety goals into concrete design constraints, safety mechanisms, and verification strategies.
Lead development of a Software Test Library (STL) for Xtensa to exercise safety mechanisms and processor resources, targeting high diagnostic coverage for each FMEDA block and supporting safety metrics such as SPFM and LFM. Contribute to FMEDA planning and analysis by providing STL‑based fault detection data, helping demonstrate compliance with ASIL-B/ASIL-D targets for the overall safety architecture.

Functional SafetyDCLS

Design Engineer II

Nov 2020 – Jul 2023 · 2 yrs 8 mos · On-site

Contributed to the Xtensa Design Verification team with a focus on the memory management unit (MMU), actively involved in verification planning, test development, and defect analysis to ensure robust MMU functionality. Held end-to-end ownership of the Interrupt Architecture for Xtensa, responsible for designing and validating interrupt handlers, crafting comprehensive tests, and building verification architectures that thoroughly cover diverse interrupt scenarios within the processor pipelines.
Led the management and delivery of IPXACT and IJTAG standards compliance for Xtensa, overseeing development and integration to support tooling, automation, and debug infrastructure.

Memory Management UnitInterrupt ArchitectureDesign Verification

Sifive

2 roles

Engineer VLSI -I

Promoted

Jan 2020 – Nov 2020 · 10 mos · On-site

Contributed to the SiFive SoC integration team, integrating diverse IP blocks to enable initial Linux bring-up on SiFive's proprietary RISC-V processors, supporting high-performance, Linux-capable core complexes for embedded and datacenter applications.
Led verification efforts for SoC integrations by developing UVM testbenches and functional tests targeting key bus protocols including AXI and APB, ensuring protocol compliance, data integrity, and interoperability across target RISC-V subsystem.

System on a Chip (SoC)AXISoC Integration

Engineer VLSI

Jul 2018 – Jan 2020 · 1 yr 6 mos · On-site

Owned verification of PCS (Physical Coding Sublayer) and FEC (Forward Error Correction) modules within Ethernet IP, developing targeted UVM testbenches to validate encoding, scrambling, alignment, and error correction mechanisms per IEEE 802.3 standards.
Developed comprehensive bus functional models (BFMs), drivers, and monitors in UVM to drive and observe full Ethernet IP functionality, enabling protocol-compliant transactions, error injection, and real-time protocol checks across MAC-to-PHY interfaces.
Achieved RTL coverage closure through constrained-random and directed testing, ensuring high functional coverage of PCS/FEC blocks, lane management, and fault scenarios to meet design quality targets for high-speed Ethernet deployments.

EthernetUniversal Verification Methodology (UVM)Ethernet Verification