Sai Teja

Software Engineer

Bengaluru, Karnataka, India8 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8 years of experience in IP and subsystem verification.
Expert in SystemVerilog programming and UVM methodology.
Achieved 100% coverage closure in multiple projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in IP and subsystem verification.

Contact

Skills

Core Skills

HbmDdrUniversal Verification Methodology (uvm)Application-specific Integrated Circuits (asic)Sv

Other Skills

DfiFunctional SafetyCache CoherencySystemVerilogPerlVery-Large-Scale Integration (VLSI)System on a Chip (SoC)LTEVerilogAXIAMBA AHBAPBCosim verificationSdfRal

About

8 years of experience in IP , Subsystem , Bus and modem verification. Worked on test bench development from scratch for multiple IPs.Hands on experience on HBM4E subsys verification. Strong Firsthand experience in System verilog programming and UVM methodology.

Experience

8 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

3 yrs 9 mos

Current Experience

Mediatek

2 roles

Staff Engineer

Jun 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

Worked on subsys test bench bringup and verification for HBM4E from end to end.
Developed test bench from scratch for AXI EDC WRAPPER and achieved 100% coverage closure as part of automotive project
Integrated FuSA(ISO 26262) changes to multiple IPs and successfully completed verification

HbmDdr

Senior Engineer

Jul 2022 – Jun 2024 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

1. worked on Cache coherence AXI Lite protocol specialised in Distributed Virtual Memory verification using cadence VIP
2. Worked on Infra Red transmitter CPIP verification
3. Hands on experience on CDC , VCS SDC verification
4. Worked on Functional Safety verification
5. worked on xprop , formal wdr verification

Xeliumtech solutions

Senior Verification Engineer

Apr 2022 – Jun 2022 · 2 mos · Bengaluru, Karnataka, India · On-site

Universal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)

Teamlease services limited

Senior Verification Engineer

May 2020 – Apr 2022 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

2 years of experience in BUS verification and IP level verification
Work experience:
1. Worked on complex Infra Bus Verification with AXI,AHB & APB protocols.
2. Hand's on experience on constraint driven verification
3. Achieved 100% coverage closure for feature test verification of Device APC(security module).
4. Developed AIP for DPTX that ensured to hit corner case scenarios.
5.Worked on ADSP subsystem verification.
6. Good knowledge on RAL verification
7. Worked on complex bus IP verification

Universal Verification Methodology (UVM)SV

Mbit wireless private limited

Phy Verification Engineer

Sep 2017 – Apr 2020 · 2 yrs 7 mos · Chennai, Tamil Nadu, India

2+ years of experience in phy verification of modem.
Work experience:
1. Worked on downlink procedures such as PDCCH & PDSCH.
2. Developed checkers with the help of perl script.
3. Hand's on experience in co-simulation verification and SDF verification.
4. Worked on low power verification features like power shut down, clock gating.
5. Worked on reset recovery and error recovery verification.

Universal Verification Methodology (UVM)SV