Apr 2017 – Aug 2017 · 4 mos · Silicon Valley and Mumbai Area, India

• Led Analytics organizational health transformation across 40 casino and hotel properties for leading hospitality client
• Drove digital strategy for invoice discounting and SME credit lending for FinTech Client
• Led initiative to accelerate loan disbursal rate by 10x with specific focus on SME lending across India

Mar 2017 – Apr 2017 · 1 mo · Mumbai Area, India

• Designed market entry strategy for Reliance's niche product to target 100M + rural consumers
• Conducted market analysis interviewing 100+ distributors and retailers across rural Maharashtra to identify potential partners and channels
• Architected strategic partnership initiatives for launching Reliance Jio 4G VoLTE smart feature phones and performed cost-benefit analysis for each alliance

Aug 2014 – Aug 2016 · 2 yrs · Mountain View, California

• Summary:
•  Spearheaded RTL design for confidential H/W products in ~$8B critical market of Android, Chromebook and Data Centers
•  Saved ~$2M for Google’s proprietary SOCs by achieving golden prototype in first production launch; Patent pending
•  Evaluated market designs for VR (virtual reality) devices, accelerating cost optimizations by ~10x for electronic integrations
•  Created fully executable multi-cached Virtual Memory with higher Prefetch hits in quick 3 months’ time from scratch
•  Orchestrated architectural design, verification and post-Silicon validation for Cloud Security project with team of 10+ experts
•  Initiated and led team of 7 PhDs to achieve 100% Lint clean design, effecting on-time delivery of Testable product to customers
•  Hired as the youngest designer in unit of 150 experts; promoted within 1st year. Received multiple Spot Bonuses and Peer Award
•  Mentored aspiring girls and minority students through Google for Education initiatives; Speaker at multiple Career Panels
•  Coordinated Govt. delegates and Media for Indian Prime Minister Modi’s Google visit; represented Google at National Interviews
• Technical Summary:
• Lead designer for critical components in Android Hardware Team : Cloud Security and Image Processing projects.
• Actively participated in FPGA emulation, Setting up digital CAD tool flow, Design verification and Post Silicon debugging.
• Documented the Architecture; coordinated agreement with the verification team and external customers.
• Implemented the design in RTL,integrated the blocks into the main base along with its analog counterpart, Performed design verification and critical bug fixes during Post Silicon debugging

Apr 2013 – Aug 2014 · 1 yr 4 mos · Santa Clara, California

• Summary:
•  Designed and optimized Power-Area to 8x Performance/Watt and 22% transistor reduction for Intel’s Knight Landings project and USA’s next Supercomputer Aurora and Trinity- 8 billion transistor chip yielding stupendous performance of 6TeraFlops
•  Coordinated team of 40+ verification, backend and arch across sites (PDX, SC, Barcelona) to resolve critical timing paths by 50%
•  Awarded Knights Armor for saving 6-month market launch delay of High Performance Computing Xeon-Phi Processors
•  Received Excellence Award for innovating Hybrid Instruction Decoder Architecture facilitating high Performance/Watt model at 1.5 GHz frequency, two-way Superscalar architecture with 38% area reduction; patent pending and fast-tracked promotion
•  Organized knowledge sharing sessions with Skylake and Knights-Hill project managers to boost cross-product compatibility
•  Served as Creative Chair and Lead-Choreographer, Intel India Employee Group, 2013-14 and Manam-Visweta Fundraiser Events
• Technical Summary:
• Optimized the power-area consumption for threaded new-AVX supportive hybrid decoder and geared the product for timely tapeout release.
• Conducted in-depth spec analysis and RTL coding for Instruction Decoder Unit
• Served as designer for core strategies in Front End of Xeon Phi - next generation (Knight's Landing Product)
• Optimizated timing critical speed paths along with power and area.
• Coordinated verification for the above-mentioned blocks with Lintra, CDC tool and coverage check
• Led cross-site coordination across Barcelona' Architecture Team, Hillsboro's Verification and Santa Clara's BackEnd Teams

Jun 2011 – Mar 2013 · 1 yr 9 mos · Santa Clara, California

• Led designing and implementation for Branch Predictor Algorithm
• Developed alternate algorithm for timing crunched decoder paths
• Designer for core strategies in Intel's Knight's Landing Project
• Actively contributed to verification and debugging for the Front End blocks.

Jun 2010 – Sep 2010 · 3 mos · Santa Clara, California

• Summary:
• Actively contributed to Post-silicon Validation and BringUp of GPU chips under different PVT corners.
• Details:
• Post Silicon Validation and Bringup of Notebook GPU chip.
• PLL Qual, Spread spectrum and Spread Qual under PVT variations.

Jan 2009 – Jun 2009 · 5 mos · Fontainebleau, France

• Summary:
• Designed database models for analyzing open-end funds & implemented parent-company-match algorithms.
• Details:
• Under the guidance of Prof Massimo Massa, Rothschild Professor of Banking.
• Analysis of open end funds and database management of parent companies.
• Counter check of datasets obtained from matching algorithm processing.

Jul 2008 – Dec 2008 · 5 mos · Pilani

• For the course of Microelectronic Circuits under the guidance of Dr. Anu Gupta, Dept. of Electrical and Electronics, BITS-Pilani.
• Tutored undergraduate students with course work and assignments.
• Graded assignments and lab tests and prepared questions.
• In addition, Assisted Dr.Borris Murman to grading several Analog courses at Stanford University, 2009-2011.

May 2008 – Aug 2008 · 3 mos · Bangalore

• Summary:
• Researched on industrial ADC designs and submitted recommendations for adoption of CT Sigma-Delta model.
• Details:
• Interned with Analog Design Group
• Analysis of Continuous Sigma Delta Modulation and present trends in Industry.
• Designed and modeled one general model using Octave and LT spice.

Jun 2007 – Jul 2007 · 1 mo · Mumbai Area, India

• Testing of High Speed ADC add on card using FPGA and Verilog.
• Debugged FPGA cards and Verilog drivers for real-time failures.