Priyanka Bhosle — Software Engineer

Good understanding of ASIC design flow. Good knowledge of static timing analysis concepts. Experience in Floorplan,Powerplan(IR-drop analysis with given target), APR(Placement,CTS,Routing) and Physical verification(DRC,LVS using Calibre and Hercules tool). Worked on improving global congestion by various placement blockages and analyzed timing reports for various paths. Experience in placement with respect to timing closure,timing optimization and low congestion. Basic Knowledge of Antenna effect,Electromigration,Crosstalk,ESD,Signal integrity and scan chain technique in DFT. Familiar with Perl and TCL scripting languages. Proficient user of Synopsys Tool Suite (ICC/Primetime). Working Knowledge of LINUX ,Verilog and C++ /C programming.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and physical design.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 5 mos