Sheshu Tayyala — Software Engineer

I am a skilled RTL Design Engineer with 2.5 years of experience at MediaTek Bangalore, specializing in RTL design, DFT, and IP/subsystem integration for advanced process nodes. I have a deep understanding of front-end digital design, verification, and quality assurance, ensuring high-performance and reliable SoC architectures. With expertise in RTL coding, design verification, ATPG, and testability optimization, I excel at developing scalable and efficient solutions for complex semiconductor designs. My ability to debug design issues, enhance test coverage, and optimize design flows has contributed to improving design efficiency, functionality, and performance. 🔹 Core Expertise & Technical Skills: ✔ RTL Design & Integration – Developing high-performance RTL using Verilog/SystemVerilog. ✔ IP & Subsystem Development – Worked on DSCE (Data Stream Compression Encoder Wrapper), Infra Debug Monitor, and SDA (System Debug Architecture). ✔ Front-End Quality Checks – Hands-on with Lint, CDC, CLP, SG-DFT, PA, ensuring design accuracy and compliance. ✔ DFT & ATPG Optimization – Improving fault coverage and testability, ensuring robust and manufacturable designs. ✔ Debugging & Functional Pattern Development – Strong ability to analyze and debug design-related tests, enhancing efficiency. ✔ Bus Protocols & SoC Integration – Proficient in AXI, AHB, APB, ATB, enabling seamless communication in complex SoC environments. ✔ Scripting & Automation – Experience in Python and Shell scripting, streamlining design verification workflows. Passionate about optimizing digital designs, ensuring correctness through rigorous quality checks, and contributing to cutting-edge SoC architectures. Open to networking, collaboration, and new opportunities in RTL design and front-end VLSI development.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in RTL and DFT for advanced process nodes.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 8 mos