Sunil Kumar Vijay Kumar

CEO

Malmo, Skåne County, Sweden20 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

18+ years in ASIC/FPGA design and validation.
Expert in SoC integration and timing analysis.
Strong scripting skills for automation in application engineering.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and FPGA technologies.

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Skills

Core Skills

Asic Rtl DesignFpga Prototyping

Other Skills

AMBA protocolsActive DirectoryCC++DFT methodologiesDebuggingFPGA design flowField-Programmable Gate Arrays (FPGA)IntegrationLogic SynthesisNetworkingProduct ValidationRTL DesignSynthesisTiming Analysis

About

18+ years of extensive diversified experience in the field of ASIC/FPGA RTL Design, Integration, Synthesis, Timing Analysis and FPGA Prototyping Development: Experience in development of RTL Design, FPGA Prototyping, SOC Design and Pre-Silicon Validation. Application Engineering : Multiple years of experience in qualification and validation of various SOC designs with great scripting skills for automation. Interest and knowledge in Firmware, Model and RTL verification flows. Degree: Masters in VLSI Design from B.M.S.C.E VTU

Experience

Ericsson

ASIC Integration Lead

Aug 2018 – Present · 7 yrs 7 mos · Kalmar County, Sweden · On-site

18+ years of extensive diversified experience in the field of ASIC RTL Design, Integration, Synthesis, Timing Analysis and FPGA Prototyping
 Successfully led the integration of a complete SoC by coordinating efforts across global cross-functional IP development teams and working closely with SoC Arch teams to define ASIC requirements, ensuring targets for performance, power, and area were met.
 Collaborated extensively with physical design and verification teams to identify and resolve RTL design and integration issues, streamline workflows, and implement required functionality for the delivery of high-quality designs.
 Responsible for defining SoC Architectural documents including the Pin list, Memory list, Address Mapping, SoC top level signals/ports connectivity list and AXI Interconnect Specifications
 Skilled in RTL Design, Logic Synthesis of complex SoC Designs with a strong understanding of timing optimization concepts and design techniques
 Integrated various IPs into the SoC top-level RTL, defining and managing interfaces between IP blocks to ensure smooth assembly, seamless data flow, and optimal performance and reliability across the system.
 Defined and managed timing constraints at the SoC top level, conducting timing analysis and closure to identify and resolve timing issues across multiple domains and clock regions, ensuring optimal performance and design functionality.
 Skilled in designing CoreLink NIC-400 AXI Network Interconnect using ARM Socrates tool with strong expertise in AMBA protocols, including AXI4, AXI3, AHB, and APB
 Strong understanding of DFT methodologies, including Scan Insertion, Memory BIST, Logic BIST, and Boundary Scan
 Hands-on expertise in the complete FPGA design flow, including RTL design and verification, synthesis, place and route (P&R), timing closure, functional verification, and board-level debugging and validation.