Suyash Bagadia

Product Engineer

Bengaluru, Karnataka, India6 yrs 8 mos experience

Highly Stable

Key Highlights

5+ years of ASIC Design Verification experience
Expert in UVM and SystemVerilog environments
Proven track record in isolating critical design bugs

Stackforce AI infers this person is a Semiconductor Design Verification Engineer with expertise in ASIC and UVM methodologies.

Contact

Skills

Core Skills

Asic Design VerificationUvmSystemverilogSoftware DevelopmentTeaching

Other Skills

C++Ethernet MACPCSFECSerDesTCLMySQLAndroid StudioAndroid DevelopmentCadence VirtuosoEtherNet/IPApplication-Specific Integrated Circuits (ASIC)VerilogUniversal Verification Methodology (UVM)Python (Programming Language)

About

I am a B.TECH (EEE) graduated from BITS and currently working on ASIC Design Verification in Cisco and over my tenure here i have worked on multiple ASIC’s/SOC verification like FC-ASIC's/ NICs and smart NIC ASIC's I have over 5+ years of experience with following: • Hands on experience on Networking protocols like Ethernet MAC/PCS/FEC/Serdes. • Good understanding of multiple bus protocols like NSPI/DHS • Hands on Experience in working and coordinating with vendor IP’s/VIP’s and cross functional team. • Defining and developing UVM/System Verilog verification environment/Testbench • Going over design specs and coming with verification plan, Attributes/test-plan definition • Owning end to end DV tasks from Testbench planning, developing ENV components from scratch, coding test cases, writing constraints/assertions, running simulations, regression analysis/debug and achieving all coverage goals • Writing Directed and Random Test scenarios • Running x-prop , Gatesims • Functional and Code coverage analysis • Working on different stages of verification i.e. Module/Block, Cluster and Chip/Top level • Post-silicon bringup of ASIC/board in lab using C++/TCL/Python scripts Over the years I have Isolated many critical bugs in design using randomness and directed testing which ensured a quality RTL tape-out .I possess strong debugging and analytical skills and also have independent problem-solving ability.

Experience

6 yrs 8 mos

Total Experience

5 yrs 8 mos

Average Tenure

1 yr

Current Experience

Cisco

2 roles

ASIC Verification Engineer

Aug 2019 – Apr 2025 · 5 yrs 8 mos · Bengaluru, Karnataka, India

Title: 400G Smart NIC ASIC’s
Extended and enhanced existing verification environment in UVM for block including Ethernet MAC/PCS/FEC/Serdes layer
Worked with multiple Vendor IP’s like COMIRA UMAC for MAC/PCS functionality, MediaTek & Broadcom for PHY Serdes, multiple Cisco in-house IP’s
Integrated and used Ethernet High speed Synopsis Verification IP (1G SGMII to 400G)
Worked on multiple bus protocols like NSPI/DHS
Developed performance infra from scratch for Bus protocols like NSPI, which was used at module/cluster/top level for Bandwidth monitoring
Time and memory-based simprofile analysis using Synopsys profile report tool to find simulation bottleneck
Developed python script for regression error parsing
Owned end to end DV tasks from Testbench planning, developing ENV components from scratch, coding test cases, writing constraints/assertions, running simulations, regression analysis/debug and achieving all coverage goals
Title: 200G NIC ASIC’s
Developed UVM based Env architecture and test plan from scratch for a XBAR buffer block and handed it over
Bring up of 50G Serdes in simulation by working and coordinating with different vendor IP/VIP teams
Created Init routines for Serdes Auto-negotiation and Link training which served as golden routine in Lab bring up and testing
Title: 64G Fiber Channel ASIC’s
Developed a System Verilog environment and testbench to verify Memory block
Developed TCL scripts to support the bring-up process
Setup GLS environment for multiple blocks and ran gate-level simulations and debugged issues, resolving critical
design problems and improving performance

SystemVerilogC++ASIC Design VerificationUVM

ASIC Engineer (Intern)

Jul 2018 – Dec 2018 · 5 mos · Bengaluru, Karnataka, India · On-site

Title: 64G Fiber Channel ASIC’s (Intern)
Time and memory-based simprofile analysis using Synopsys profile report tool to find simulation bottleneck
Handled running regression at module, sub-chip and chip level

Adani power

Intern (Software developer)

May 2017 – Jul 2017 · 2 mos

During this period of time i underwent rigorous training and developed an Android application for monitoring the maintenance parameters of switch yard for electrical department.l also helped in developing a data retrieval software using MySQL

MySQLAndroid StudioSoftware Development

Birla institute of technology and science, pilani

2 roles

Undergraduate Teaching Assistant

Jan 2017 – May 2017 · 4 mos

Conducted Laboratory tutorials for the students for Microelectronic Circuits course and helped them in the design of basic amplifier configurations in Cadence Virtuoso

Cadence VirtuosoTeaching