amith patil

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience
Highly Stable

Key Highlights

  • Certified in VLSI design and verification.
  • Staff Engineer at MediaTek since 2019.
  • Strong foundation in digital electronics and verification methodologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in verification methodologies.

Contact

LinkedIn

Skills

Core Skills

VerilogUniversal Verification Methodology (uvm)

Other Skills

System verilogEngineeringC (Programming Language)C++LeadershipTeamworkXilinx ISEDigital Electronics

About

Fresher 2018 pass out.Have a certification in VLSI design and verification.

Experience

6 yrs 9 mos
Total Experience
6 yrs 9 mos
Average Tenure
6 yrs 9 mos
Current Experience

Mediatek

Staff Engineer

Jul 2019 – Present · 6 yrs 9 mos · Karnataka, India

VerilogSystem verilogUniversal Verification Methodology (UVM)EngineeringC (Programming Language)C+++4

Education

M V J College of Engineering, BANGALORE

Bachelor of Engineering — Electronics and Communications Engineering

Jan 2014 – Jan 2018

Chetan PU Science College , Hubli

PUC — science

Jun 2012 – Jul 2014

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