Sudheer Reddy — Software Engineer

 Good understanding of the ASIC design flow  Extensive experience in writing RTL models using Verilog HDL.  Good experience in writing Test benches using SystemVerilog and UVM  Very good knowledge in verification methodologies  Experience in using industry standard EDA tools for the front-end design and verification

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on ASIC and VLSI verification.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 10 mos