Shriyash G.

DevOps Engineer

Bengaluru, Karnataka, India7 yrs 7 mos experience

Highly Stable

Key Highlights

Five years of expertise in pre-silicon verification.
Strong proficiency in UVM and SVA.
Implemented assertion-based verification techniques.

Stackforce AI infers this person is a Verification Engineer specializing in digital design and functional verification methodologies.

Contact

shriyashgadve07@gmail.com LinkedIn

Skills

Core Skills

Functional Verification

Other Skills

Microsoft WordMicrosoft ExcelCMatlabMicrosoft OfficeResearchMicrocontrollersEmbedded CVerilogSignal ProcessingPerlTcl-TkSystemVerilogCadence VirtuosoStatic Timing Analysis

About

I am an experienced verification engineer with five years of expertise in simulation-based pre-silicon verification. My background includes a strong proficiency in Universal Verification Methodology (UVM) and SystemVerilog Assertions (SVA), enabling me to develop robust verification environments. I have successfully implemented assertion-based verification techniques to identify and resolve complex design issues early in the development cycle. My hands-on experience includes creating comprehensive testbenches and employing advanced verification methodologies to ensure design reliability and performance. With extensive experience in reset flow and power management (PM) flow of UCIE (Universal Chiplet Interconnect Express), I am also well-versed in digital PHY verification. I continuously strive to enhance verification processes, ensuring high-quality deliverables. With a keen eye for detail and a passion for innovation, I am committed to driving excellence in verification.

Experience

7 yrs 7 mos

Total Experience

3 yrs 2 mos

Average Tenure

1 yr 6 mos

Current Experience

Nvidia

Senior Verification Engineer

Oct 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

SoC Design Engineer

Jul 2020 – Jan 2025 · 4 yrs 6 mos · Bengaluru, Karnataka, India

𝙡𝙚𝙖𝙧𝙣𝙞𝙣𝙜/ skill gained :
➡Analyze specification and finding out interesting scenarios.
➡Creating Testplan.
➡Learn to make use of code coverage and functional coverage to understand holes in the plan.
➡Debugging skills.
➡Interesting Glimpse of Formal verification.
𝙬𝙤𝙧𝙠 𝙨𝙪𝙢𝙢𝙖𝙧𝙮 / my contribution :
➡ UVC
Following feature validation.
➡Resets.
➡Power Management of flows.
➡Error injection capability, recovery after error scenarios.
➡Timers.
Interface worked on PIPE, AMBA Low power.