May 2019 – Dec 2020 · 1 yr 7 mos · Greater Bengaluru Area

Sep 2014 – May 2019 · 4 yrs 8 mos · Bangalore

• Functional verification of HBM PHY IP using system verilog and UVM.
• Gate level simulations, Co simulations for HBM PHY IP.
• Integration of HBM Controller+PHY+Memory.
• DFI VIP integration with LPDDR PHY and verification of LPDDR using system verilog and UVM.
• Formal verification of DDR PHY's MTEST MUX using VCF formal tool.
• DDR PHY device initialization using firmware and dummy micro controller.
• Owned HBM Memory (memory model as well as VIP) integration and verification of PHY+Memory.
• Owned PRBS based loopback verification.
• Implemented interposer for delay insertion between PHY and Memory.
• Responsible for DBI generation logic inside scoreboard and writing checkers for DBI.
• Owned testbench implementation for HBM testchip verification.

Sep 2013 – Sep 2014 · 1 yr · Bangalore

• Functional verification of HBM PHY IP using system verilog and UVM.
• DFT features verification of HBM PHY IP using P1500 protocol.
• Converted sequences to support virtual sequencer approach.
• Implemented reconfigure method learnt from VIP verification for on the fly changes.
• Provided backdoor support for RAL model and testing of RAL model through UVM inbuilt sequences.
• Owner of cosim(analog+digital) and GLS simulations across all revisions.
• Owned DFT feature verification (internal loopback, highz, clock stop) using P1500 protocol.
• Got a chance to work on RTL coding for correcting pointer separation logic of pipelines during loopback mode.

Jul 2010 – Aug 2013 · 3 yrs 1 mo · Greater Ahmedabad Area

• Functional verification of AXI and MIPI M-PHY VIPs using UVM and system verilog.
• AXI:
• Owned sequence library to cover every corner scenario.
• Responsible for feature verification like unaligned address generation, parallel read writes, wstrb possible combinations etc. to name a few.
• Owned slave memory model verification.
• Integration of protocol analyser tool and enabling other team members to start using it.
• Implemented TLM port infra for HDL (verilog wrapper) to pass transaction from verilog to system verilog components.
• Owner of proving multisim (VCS,Incisive,Questa) support across environment.
• M-PHY:
• Modified existing testbench to be UVM compliant.
• Created virtual sequence library for multilane environment.
• Owned multilane environment and RMMI (parallel) interface.
• Responsible for developing and maintaining FSM status monitor logic.
• Implementation owner for auxiliary signal support to enter and exit from HIBERNATE.
• Owner of model environment (RMMI to serial conversion).
• Developed exception (way to insert errors from driver level) insertion infra.
• Owned all scoreboards across all topologies Serial,RMMI and model env.

Jan 2010 – Jul 2010 · 6 mos · Kutch

• Control room engineer in a power generation organization.