Aug 2022 – Feb 2026 · 3 yrs 6 mos · Bengaluru, Karnataka, India

• Accelerator NoC routers uArch/RTL design for 2Ghz clk
• Address Translation Cache uArch/RTL design.
• Temperature telemetry uarch/design

Oct 2020 – Aug 2022 · 1 yr 10 mos

• ARM Multichip SoC Verification
• TB architecture development and RTL verification of multichip SoC targeted for arm's server market.
• > Developed FE TB flow methodology for multichip environment.
• > Boot code for init programming of the system.
• > Complete programming of coherent mesh network for multichip system.
• > Developed multiple test cases with C and UVM for verifying timestamp synchronisation, xchip message handling , xchip interrupts and DVM ops from local CPUs targeting remote chips' SMMUs.
• >Developed fast boot methodologies to bypass the slow sw boot
• Inhouse IP stitching tool
• Developed an inhouse tool for automated integration/stitching of IPs using Python, thereby reducing the turnaround time to develop the system based on specifications and test it seamlessly.

Jul 2019 – Oct 2020 · 1 yr 3 mos

• Design Verification of NoC (Network on Chip) IP based on ARM's v9 arch at system level in mobile as well as infra platforms.
• Enhanced the existing ARM internal tool for automated RTL integration with PHP based APIs which requires very minimal user input to generate the final verilog files , thus increasing the readability to debug connectivity issues and increased the turn around time to build, compile as well test the systems faster.

Jan 2019 – Jun 2019 · 5 mos · India

• Juniper Networks
• Standardization of error injection tests for multiple blocks part of a fabric chip using system verilog and
• UVM.
• Enhanced ,scaled and owned the whole error injection TB .
• Worked on various other debugs and found multiple bugs.

Jul 2018 – Dec 2018 · 5 mos · Bengaluru, Karnataka, India

• Formal Verification of hardware scheduling components in a XBAR
• Developed the full environment for semi formal verification of a multi GPU connecting switch - the system would route data packets among multiple GPUs and implement arbitration among them.
• Checks were written using in-built assertions under given assumptions (constraints) and the checkers were implemented on state machines.
• Implemented 9 checks for 3 components within the switch system that tested various arbitration policies - starvation, stickiness, utilization etc.
• Developed automation scripts using Perl.

May 2016 – Jul 2016 · 2 mos · Odisha, India

• This project covers the basic orientation about Vedanta Resources. It also includes introduction to the aluminium extraction process, and detailed analysis of various in-house setups and the processes involved. The first project aims to improve the efficiency of the various motors present in the GAP plant. This is done through a thorough scrutiny of the motors currently being used and implementing techniques which help improve the efficiency of them. The second project is a maintenance project which aims to reduce the occurrence of malfunction of heater which is a very essential process in the making of green anodes.