sai Rajendra Vuppala

Software Engineer

Hyderabad, Telangana, India5 yrs 7 mos experience

Key Highlights

  • Proficient in ASIC design and verification methodologies.
  • Experienced in FPGA and hardware description languages.
  • Strong background in digital design and verification.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and FPGA technologies.

Contact

LinkedIn

Skills

Other Skills

ARINC 429Assertion Based VerificationField-Programmable Gate Arrays (FPGA)I2CUniversal Asynchronous Receiver/Transmitter (UART)Universal Verification Methodology (UVM)VHDLVerilogsystem verilog

Experience

Wipro

Senior vlsi engineer

Feb 2025 – May 2025 · 3 mos · Hyderabad, Telangana, India

Tech mahindra

Senior Engineer

Mar 2024 – Sep 2024 · 6 mos · Vishakhapatnam, Andhra Pradesh, India · On-site

Synopsys inc

Asic Digital design engineer 2

Aug 2022 – Aug 2023 · 1 yr

Einfochips (an arrow company)

Design Verification Engineer

Jan 2022 – Jul 2022 · 6 mos · Hyderabad, Telangana, India

Wipro limited

Design and verification engineer

Jun 2018 – Jan 2022 · 3 yrs 7 mos · Banglore

  • ASIC Verification engineer

Maven silicon

Internship Trainee

Feb 2018 – Jun 2018 · 4 mos · Banglore

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Micro electronics

Jan 2020 – Jan 2022

swami ramananda tritha institute of sciene and techonology nalgonda

Jan 2013 – Jan 2017

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