A

AMRITA PATIL

Software Engineer

India3 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in Digital IC design and Physical Design.
  • Proficient in automation scripting for design tools.
  • Strong foundation in Static Timing Analysis concepts.
Stackforce AI infers this person is a Digital IC Design Engineer with expertise in Physical Design and automation scripting.

Contact

LinkedIn

Skills

Core Skills

Digital Ic DesignPhysical Design

Other Skills

TCLStatic Timing AnalysisLow-power DesignCadence EncounterSynopsys ICC2Cadence VirtuosoModelSimIntel Quartus Prime

About

- Worked on entire design initialization to GDSII flow in ENCOUNTER tool with good understanding of Floorplanning, Power planning, Placement, CTS, Routing and signoff. - Designed two step rectilinear floorplan in 45nm technology node and achieved 70% utilization in Encounter tool. - Developed automation scripts for ENDCAP, TAPCELLS and FILLER CELLS insertion. - Good understanding of STA concepts like OCV, CPRR and timing fixes. - Carried out sanity checks at every stage of Physical Design and fixed errors. - Basic understanding of Low Power Design techniques.

Experience

3 yrs 11 mos
Total Experience
2 yrs
Average Tenure
0 mo
Current Experience

Qualcomm

Senior Engineer

Apr 2026 – Present · 0 mo · Bengaluru · On-site

TCLDigital IC designStatic Timing AnalysisPhysical DesignLow-power DesignCadence Encounter

Mediatek

Engineer

May 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India

Smartsoc solutions pvt ltd

Physical Design Engineer

Jun 2021 – Apr 2022 · 10 mos · Bangalore Urban, Karnataka, India

Education

Vellore Institute of Technology

Mtech — VLSI Design

Jan 2019 – Jan 2021

All India Shri Shivaji Memorial Society's Institute of Information Technology, Pune

Bachelor of Engineering - BE — Electronics and Telecommunication

Jan 2013 – Jan 2017

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