Hareesh Kanneboina.

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience

Highly Stable

Key Highlights

Delivered 8+ subsystems successfully.
Expert in low-power synthesis and timing closure.
Hands-on experience with multiple IPs at MediaTek.

Stackforce AI infers this person is a VLSI Engineer with expertise in digital design and synthesis.

Contact

kanneboina.hareesh@gmail.com LinkedIn

Skills

Core Skills

SynthesisSta & Timing EcosConformal Lec

Other Skills

PrimetimeTweakerGenusCerebrusCLPTessent EDTSynopsys PrimetimePhysical DesignDigital ElectronicsVerilog HDLDigital IC DesignCadence VirtuosoPerlTCLElectronic Engineering

About

VLSI Engineer with 2+ years of experience in Synthesis, STA, Timing Closure, Low-Power Checks, QC flows at MediaTek. Hands-on expertise across ISP and DISPLAY IPs, with ownership of block-level and top-level synthesis, STA signoff, and flow setup. I have delivered 8+ subsystems, coordinated multi-block integration, executed MMMC synthesis, performed DFT integration, improved ATPG coverage, and driven timing closure using Primetime & Tweaker. Key strengths include: ✔ Synthesis (Genus, DC, Cerebrus PPA trials) ✔ STA & Timing ECOs (Primetime, Tweaker) ✔ LEC & Low-Power Checks (CLP) ✔ DFT/ATPG (Tessent EDT) ✔ QC flows: ERC, CCF, PreSTA, Clock structure checks ✔ Automation using TCL, Perl & C-shell

Experience

2 yrs 9 mos

Total Experience

2 yrs 9 mos

Average Tenure

2 yrs 9 mos

Current Experience

Mediatek

2 roles

Senior Engineer

Jul 2023 – Present · 2 yrs 9 mos · Bengaluru, Karnataka, India · On-site

perform STA & timing closure using Primetime & Tweaker.
Execute low-power logical & physical synthesis using Genus / Cerebrus for subsystems and/or top-design. Includes Synthesis & QC flow setup & provide support for other Block owners.
Perform Conformal logical equivalance check (LEC), Conformal Low power check (CLP) - for Subsys/top.
Perfom ERC, CCF, Pre-STA, timing-vision SDC checks & clock tree structure checks.
Perfom DRC check, ATPG coverage improvement and DFT verification using Tessent EDT.

PrimetimeTweakerGenusCerebrusConformal LECCLP+3