Pavan Yeluri

Product Manager

Bengaluru, Karnataka, India19 yrs 8 mos experience

Highly Stable

Key Highlights

18+ years in ASIC/FPGA/SoC Verification
Best paper award at DAC 2020
Expertise in Pre & Post Si Validation

Stackforce AI infers this person is a highly experienced ASIC/FPGA verification engineer with a strong focus on SoC and memory controller systems.

Contact

Skills

Core Skills

System On A Chip (soc)VerificationAsic Verification

Other Skills

Altera QuartusApplication-Specific Integrated Circuits (ASIC)C (Programming Language)C++CVSDDRDDR2-SDRAMField-Programmable Gate Arrays (FPGA)Formal VerificationFormal verificationFunctional VerificationGDDR6Gate Level SimulationHBMHBM3

About

18+ years hands on experience in ASIC/FPGA/SoC Verification. Currently working on Fabric/NoC Subsystem verification. Previously worked on IP , Sub-System, SoC level Verification & Post Si validation of HBM3 & GDDR6 Memory controller Subsystem for a Graphics SoC meant for Super Compute applications. , MIPI DSI IP(C-PHY & D-PHY), Fabrics, Boot and Power management Sub System, Always-on Sub Systems. Developed SV, UVM & C++ based verification environment from scratch. Involved in the complete life cycle of IP & SoC Level Verification and Validation. Expertise in both Pre & Post Si Validation. Skilled in verification methodologies like SV/UVM etc. Have multiple awards , paper selections at various conferences(details below) Won Best paper award in DAC 2020 in 'Designer Track Front-End' for the following paper:- 1) 'Achieve Better Communication In Your UVM TB Using These Obscure UVM Classes'(Main author/speaker) Have following 2 paper selections at DVCON India 2019:- 1) 'Using Software Design Patterns in Test Bench Development for a Multi-Layer Protocol' (Main author/speaker) 2) 'Adaptive UVM <-> AMOD(C++ based algo. model) testbench for configurable DSI IP' (Co-Author) Have 1 paper selection at DAC 2021:- Get more out of your UVM register layer! Have 1 poster selection at DAC 2022:- Efficient stimulus generation techniques for a UVM TB

Experience

Google

Design Verification Manager, Silicon

Oct 2023 – Present · 2 yrs 5 mos · Hybrid

DV @ Google

Intel corporation

Senior Design Verification Manager

Oct 2021 – Oct 2023 · 2 yrs · Hyderabad, Telangana, India · On-site

Hands-on role. Currently working on HBM3 memory controller Sub System & SoC level Verification . Worked on GDDR6 Sub system and Fabric Sub System before. Role involves developing UVM components and also working on Formal verification methodologies. It also involves mentoring junior members in the team, creating Verification strategy, scheduling tasks among team members, representing my Sub-systems to higher management and driving towards verification closure.

HBM3GDDR6UVMFormal verificationVerification strategySystem on a Chip (SoC)+1

Nvidia

Senior Design Verification Engineer

Feb 2018 – Sep 2021 · 3 yrs 7 mos · Hyderabad Area, India · On-site

Worked on IP level and SoC level Verification of MIPI DSI IP(C-PHY & D-PHY). Developing SV, UVM & C++ based verification environment from scratch. Involved in the complete life cycle of IP Verification and Validation. Also, working on Sub-system level , SoCV level testbench ,FPGA simulations and Post Si-validation for for Display & DSI.
Owned Unit/Sub system and SOC verification of Boot and Power management subsytem, Always-ON Subsystem/Power Management controller Sub system along with the IO subsytem(I2C/QSPI/UART/SBSA UART/PWM etc)

MIPI DSISVUVMC++Post Si-validationVerification+1

Xilinx

Senior Design Engineer (Design Verification)

Feb 2011 – Feb 2018 · 7 yrs · Hyderabad Area, India

Involved in the complete verification cycle of various IPs in Xilinx IP catalog like AXI-AHB Bridges, QuadSPI, Chip2Chip, GigaBit Transceivers(GT), SERDES , System Management IP, USB 2.0, AXI-APB Bridges, AXI4-Stream FIFO IP etc. in System Verilog, OVM & UVM

System VerilogOVMUVMVerificationSystem on a Chip (SoC)

Wipro

Module Lead(ASIC Verification), Design

Jul 2006 – Feb 2011 · 4 yrs 7 mos · Hyderabad Area, India

Worked on ASIC verification of various projects involving protocols like DDR2-SDRAM, PCI, ONFI NAND Flash, etc. Also worked on verification of complex chips like Digital Base Band Processor ASIC as a part of which completely owned blocks like Memory controllers(involving DDR,SDRAM, Nor Flash,cellular RAM,Micron Mobile DDR SDRAM etc). in Verilog , System Verilog & OVM
Also involved in verification of DMA controllers
Also did RTL Design .

DDR2-SDRAMPCIVerilogSystem VerilogOVMASIC Verification+1